Patents by Inventor Dae-ho Yoon

Dae-ho Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9334192
    Abstract: The present invention relates to a dielectric ceramic composition, method for preparing the same, and electronic device using the same. According to the present invention, there is provided a dielectric ceramic composition which allows use of a nickel internal electrode, sintering under a reducing atmosphere, and having 1000 or higher dielectric constant while providing excellent dc-bias properties and reliability which is close to paraelectric property. The composition of the present invention can generate high effective capacity under high DC voltage, have strong resistance against electrostatic discharge (ESD) damage, and be used for preparing an electronic device having low acoustic noise.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: May 10, 2016
    Assignees: SAMSUNG ELECTRO-MECHANICS CO., LTD., RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Seok-Hyun Yoon, Masaki Takaki, Yoon-Ah Roh, Dae-Ho Yoon, Chang-Hoon Kim, Doo-Young Kim
  • Publication number: 20160090325
    Abstract: The present invention relates to a dielectric ceramic composition, method for preparing the same, and electronic device using the same. According to the present invention, there is provided a dielectric ceramic composition which allows use of a nickel internal electrode, sintering under a reducing atmosphere, and having 1000 or higher dielectric constant while providing excellent dc-bias properties and reliability which is close to paraelectric property. The composition of the present invention can generate high effective capacity under high DC voltage, have strong resistance against electrostatic discharge (ESD) damage, and be used for preparing an electronic device having low acoustic noise.
    Type: Application
    Filed: March 18, 2015
    Publication date: March 31, 2016
    Inventors: Seok-Hyun YOON, Masaki TAKAKI, Yoon-Ah ROH, Dae-Ho YOON, Chang-Hoon KIM, Doo-Young KIM
  • Patent number: 9053955
    Abstract: A nitride semiconductor device includes a dislocation control layer on a substrate, and a nitride semiconductor layer on the dislocation control layer. The dislocation control layer includes a nanocomposite of a first nanoparticle made of a first material and at least one second nanoparticle made of a second material.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: June 9, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon-sang Lee, Sung-soo Park, Dae-ho Yoon
  • Patent number: 9054234
    Abstract: A nitride semiconductor device may include a substrate, a dislocation control layer formed on the substrate and including a plurality of hollow structures including a nitride, and a nitride semiconductor layer formed on the dislocation control layer.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: June 9, 2015
    Assignees: SAMSUNG ELECTRONICS CO., LTD., RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Moon-Sang Lee, Sung-Soo Park, Bong-Kyun Kang, Dae-Ho Yoon
  • Publication number: 20150125982
    Abstract: A nitride semiconductor device may include a substrate, a dislocation control layer formed on the substrate and including a plurality of hollow structures including a nitride, and a nitride semiconductor layer formed on the dislocation control layer.
    Type: Application
    Filed: October 23, 2014
    Publication date: May 7, 2015
    Inventors: Moon-Sang LEE, Sung-Soo PARK, Bong-Kyun KANG, Dae-Ho YOON
  • Patent number: 8952423
    Abstract: A semiconductor device includes a logic region disposed in a central region of the semiconductor device, and a peripheral region disposed in an outer region thereof. The logic region includes a line-shaped logic transistor and a box-shaped decoupling capacitor. The peripheral region includes a line-shaped peripheral transistor and a line-shaped peripheral dummy transistor disposed adjacent to the peripheral transistor.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joong-Won Jeon, Hee-Sung Kang, Dae-Ho Yoon, Dal-Hee Lee, Suk-Joo Lee
  • Publication number: 20140061587
    Abstract: A nitride semiconductor device includes a dislocation control layer on a substrate, and a nitride semiconductor layer on the dislocation control layer. The dislocation control layer includes a nanocomposite of a first nanoparticle made of a first material and at least one second nanoparticle made of a second material.
    Type: Application
    Filed: February 20, 2013
    Publication date: March 6, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Moon-sang LEE, Sung-soo PARK, Dae-ho YOON
  • Publication number: 20130320405
    Abstract: A semiconductor device includes a logic region disposed in a central region of the semiconductor device, and a peripheral region disposed in an outer region thereof. The logic region includes a line-shaped logic transistor and a box-shaped decoupling capacitor. The peripheral region includes a line-shaped peripheral transistor and a line-shaped peripheral dummy transistor disposed adjacent to the peripheral transistor.
    Type: Application
    Filed: March 5, 2013
    Publication date: December 5, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joong-Won JEON, Hee-Sung KANG, Dae-Ho YOON, Dal-Hee LEE, Suk-Joo LEE
  • Patent number: 8421326
    Abstract: An electrode including metal oxides and a plurality of 12CaO.7Al2O3 particles, a method of preparing the electrode, an electronic device including the electrode, and, in particular, an organic light emitting device including the electrode. The electrode has low resistance, high optical transmittance, and a low work function.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: April 16, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Won-Jong Kim, Yong-Tak Kim, Jong-Hyuk Lee, Dae-Ho Yoon, Seok-Gyu Yoon, Hosono Hideo
  • Patent number: 8289606
    Abstract: An optical image shutter having a transparent electro-optical crystal formed on a transparent amorphous substrate and a method of manufacturing the optical image shutter. The light image shutter is created by forming a buffer layer using a material having a similar crystalline structure to an electro-optical crystal, on a transparent amorphous substrate such as glass, and forming an electro-optical thin film layer such as the electro-optical crystal on the buffer layer.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: October 16, 2012
    Assignees: Samsung Electronics Co., Ltd., Sungkyunkwan University Foundation for Corporate Collaboration
    Inventors: Yong-hwa Park, Chul-ho Jung, Dae-ho Yoon
  • Publication number: 20110170160
    Abstract: An optical image shutter having a transparent electro-optical crystal formed on a transparent amorphous substrate and a method of manufacturing the optical image shutter. The light image shutter is created by forming a buffer layer using a material having a similar crystalline structure to an electro-optical crystal, on a transparent amorphous substrate such as glass, and forming an electro-optical thin film layer such as the electro-optical crystal on the buffer layer.
    Type: Application
    Filed: July 29, 2010
    Publication date: July 14, 2011
    Applicants: Samsung Electronics Co., Ltd., Sungkyunkwan University Foundation for Corporate Collaboration
    Inventors: Yong-hwa PARK, Chul-ho JUNG, Dae-ho YOON
  • Patent number: 7915150
    Abstract: A method of manufacturing a nitride semiconductor substrate according to example embodiments may include forming a buffer layer on a (100) plane of a silicon (Si) substrate. The buffer layer may have a hexagonal crystal system and a (1010) plane. A nitride semiconductor layer may be epitaxially grown on the buffer layer. The nitride semiconductor layer may have a (1010) plane. Accordingly, because example embodiments enable the use of a relatively inexpensive Si substrate, a more economical nitride semiconductor substrate having a relatively large diameter may be achieved.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: March 29, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-soo Park, Dae-ho Yoon
  • Publication number: 20090200913
    Abstract: An electrode including metal oxides and a plurality of 12CaO.7Al2O3 particles, a method of preparing the electrode, an electronic device including the electrode, and, in particular, an organic light emitting device including the electrode. The electrode has low resistance, high optical transmittance, and a low work function.
    Type: Application
    Filed: February 11, 2009
    Publication date: August 13, 2009
    Applicant: Samsung Mobile Display Co., Ltd.
    Inventors: Won-Jong KIM, Yong-Tak KIM, Jong-Hyuk LEE, Dae-Ho YOON, Seok-Gyu YOON, Hosono HIDEO
  • Publication number: 20090189122
    Abstract: Disclosed is a method for preparing an oxide nano phosphor. A metal precursor solution is prepared. The metal precursor solution is impregnated into a porous polymer material. A heat treatment is performed on the porous polymer material having the metal precursor solution impregnated therein. The heat treatment is performed by heating the porous polymer material having the metal precursor impregnated therein up to a temperature of higher than 500° C. solution at a temperature elevating rate of higher than 100° C. per minute.
    Type: Application
    Filed: May 29, 2008
    Publication date: July 30, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Tae-gon KIM, Dae-ho YOON, Takaki MASAKI, Woo-jung PARK, Mong-Kwon JUNG, Seoung-jae IM
  • Publication number: 20090191695
    Abstract: A method of manufacturing a nitride semiconductor substrate according to example embodiments may include forming a buffer layer on a (100) plane of a silicon (Si) substrate. The buffer layer may have a hexagonal crystal system and a (1010) plane. A nitride semiconductor layer may be epitaxially grown on the buffer layer. The nitride semiconductor layer may have a (1010) plane. Accordingly, because example embodiments enable the use of a relatively inexpensive Si substrate, a more economical nitride semiconductor substrate having a relatively large diameter may be achieved.
    Type: Application
    Filed: July 10, 2008
    Publication date: July 30, 2009
    Inventors: Sung-soo Park, Dae-ho Yoon