Patents by Inventor Daehong Eom
Daehong Eom has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9972638Abstract: Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided.Type: GrantFiled: February 13, 2015Date of Patent: May 15, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sunghae Lee, Daehong Eom, JinGyun Kim, Daehyun Jang, Kihyun Hwang, Seongsoo Lee, Kyunghyun Kim, Chadong Yeo, Jun-Youl Yang, Se-Ho Cha
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Patent number: 9899411Abstract: A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.Type: GrantFiled: January 24, 2017Date of Patent: February 20, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dongchul Yoo, Phil Ouk Nam, Junkyu Yang, Woong Lee, Woosung Lee, JinGyun Kim, Daehong Eom
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Publication number: 20170133400Abstract: A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.Type: ApplicationFiled: January 24, 2017Publication date: May 11, 2017Inventors: Dongchul YOO, Phil Ouk NAM, Junkyu YANG, Woong LEE, Woosung LEE, JinGyun KIM, Daehong EOM
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Patent number: 9559111Abstract: A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.Type: GrantFiled: July 2, 2015Date of Patent: January 31, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dongchul Yoo, Phil Ouk Nam, Junkyu Yang, Woong Lee, Woosung Lee, JinGyun Kim, Daehong Eom
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Patent number: 9368647Abstract: Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound material. The silicon compound material includes a silicon atom, at least one selected from the group of a nitrogen atom, a phosphorus atom and a sulfur atom combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided.Type: GrantFiled: August 12, 2015Date of Patent: June 14, 2016Assignees: Samsung Electronics Co., Ltd., Soulbrain Co., Ltd.Inventors: Young-Taek Hong, Jinuk Lee, Junghun Lim, Jaewan Park, Chanjin Jeong, Hoon Han, Seonghwan Park, Yanghwa Lee, Sang Won Bae, Daehong Eom, Byoungmoon Yoon, Jihoon Jeong, Kyunghyun Kim, Kyounghwan Kim, ChangSup Mun, Se-Ho Cha, Yongsun Ko
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Publication number: 20150348799Abstract: Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound material. The silicon compound material includes a silicon atom, at least one selected from the group of a nitrogen atom, a phosphorus atom and a sulfur atom combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided.Type: ApplicationFiled: August 12, 2015Publication date: December 3, 2015Inventors: Young Taek Hong, Jinuk Lee, Junghun Lim, Jaewan Park, Chanjin Jeong, Hoon Han, Seonghwan Park, Yanghwa Lee, Sang Won Bae, Daehong Eom, Byoungmoon Yoon, Jihoon Jeong, Kyunghyun Kim, Kyounghwan Kim, ChangSup Mun, Se-Ho Cha, Yongsun Ko
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Publication number: 20150311214Abstract: A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.Type: ApplicationFiled: July 2, 2015Publication date: October 29, 2015Inventors: Dongchul YOO, Phil Ouk NAM, Junkyu YANG, Woong LEE, Woosung LEE, JinGyun KIM, Daehong EOM
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Patent number: 9136120Abstract: Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound. The silicon compound includes a silicon atom, an atomic group having an amino group combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided.Type: GrantFiled: December 17, 2014Date of Patent: September 15, 2015Assignees: Samsung Electronics Co., Ltd., Soulbrain Co., Ltd.Inventors: Young Taek Hong, Jinuk Lee, Junghun Lim, Jaewan Park, Chanjin Jeong, Hoon Han, Seonghwan Park, Yanghwa Lee, Sang Won Bae, Daehong Eom, Byoungmoon Yoon, Jihoon Jeong, Kyunghyun Kim, Kyounghwan Kim, ChangSup Mun, Se-Ho Cha, Yongsun Ko
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Patent number: 9076879Abstract: A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.Type: GrantFiled: August 23, 2013Date of Patent: July 7, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dongchul Yoo, Phil Ouk Nam, Junkyu Yang, Woong Lee, Woosung Lee, JinGyun Kim, Daehong Eom
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Publication number: 20150162344Abstract: Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided.Type: ApplicationFiled: February 13, 2015Publication date: June 11, 2015Inventors: Sunghae LEE, Daehong Eom, JinGyun Kim, Daehyun Jang, Kihyun Hwang, Seongsoo Lee, Kyunghyun Kim, Chadong Yeo, Jun-Youl Yang, Se-Ho Cha
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Publication number: 20150104932Abstract: Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound. The silicon compound includes a silicon atom, an atomic group having an amino group combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided.Type: ApplicationFiled: December 17, 2014Publication date: April 16, 2015Inventors: Young Taek Hong, Jinuk Lee, Junghun Lim, Jaewan Park, Chanjin Jeong, Hoon Han, Seonghwan Park, Yanghwa Lee, Sang Won Bae, Daehong Eom, Byoungmoon Yoon, Jihoon Jeong, Kyunghyun Kim, Kyounghwan Kim, ChangSup Mun, Se-Ho Cha, Yongsun Ko
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Patent number: 8963231Abstract: Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided.Type: GrantFiled: February 21, 2012Date of Patent: February 24, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Sunghae Lee, Daehong Eom, JinGyun Kim, Daehyun Jang, Kihyun Hwang, Seongsoo Lee, Kyunghyun Kim, Chadong Yeo, Jun-Youl Yang, Se-Ho Cha
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Patent number: 8940182Abstract: Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound. The silicon compound includes a silicon atom, an atomic group having an amino group combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided.Type: GrantFiled: August 31, 2012Date of Patent: January 27, 2015Assignees: Samsung Electronics Co., Ltd., Soulbrain Co., Ltd.Inventors: Young-Taek Hong, Jinuk Lee, Junghun Lim, Jaewan Park, Chanjin Jeong, Hoon Han, Seonghwan Park, Yanghwa Lee, Sang Won Bae, Daehong Eom, Byoungmoon Yoon, Jihoon Jeong, Kyunghyun Kim, Kyounghwan Kim, ChangSup Mun, Se-Ho Cha, Yongsun Ko
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Patent number: 8685821Abstract: A mold stack including alternating insulation layers and sacrificial layers is formed on a substrate. Vertical channel regions extending through the insulation layers and sacrificial layers of the mold stack are formed. Gate electrodes are formed between adjacent ones of the insulation layers and surrounding the vertical channel regions. The gate electrodes have a greater thickness at a first location near sidewalls of the insulation layers than at a second location further away from the sidewalls of the insulation layers.Type: GrantFiled: September 6, 2013Date of Patent: April 1, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Daehong Eom, Kyunghyun Kim, Kwangsu Kim, Jun-Youl Yang, Se-Ho Cha
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Publication number: 20140070302Abstract: A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.Type: ApplicationFiled: August 23, 2013Publication date: March 13, 2014Inventors: Dongchul YOO, Phil Ouk NAM, Junkyu YANG, Woong LEE, Woosung LEE, JinGyun KIM, Daehong EOM
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Publication number: 20140004676Abstract: A mold stack including alternating insulation layers and sacrificial layers is formed on a substrate. Vertical channel regions extending through the insulation layers and sacrificial layers of the mold stack are formed. Gate electrodes are formed between adjacent ones of the insulation layers and surrounding the vertical channel regions. The gate electrodes have a greater thickness at a first location near sidewalls of the insulation layers than at a second location further away from the sidewalls of the insulation layers.Type: ApplicationFiled: September 6, 2013Publication date: January 2, 2014Inventors: Daehong Eom, Kyunghyun Kim, Kwangsu Kim, Jun-Youl Yang, Se-Ho Cha
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Patent number: 8552489Abstract: A mold stack including alternating insulation layers and sacrificial layers is formed on a substrate. Vertical channel regions extending through the insulation layers and sacrificial layers of the mold stack are formed. Gate electrodes are formed between adjacent ones of the insulation layers and surrounding the vertical channel regions. The gate electrodes have a greater thickness at a first location near sidewalls of the insulation layers than at a second location further away from the sidewalls of the insulation layers.Type: GrantFiled: November 29, 2012Date of Patent: October 8, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Daehong Eom, Kyunghyun Kim, Kwangsu Kim, Jun-Youl Yang, Se-Ho Cha
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Publication number: 20130134493Abstract: A mold stack including alternating insulation layers and sacrificial layers is formed on a substrate. Vertical channel regions extending through the insulation layers and sacrificial layers of the mold stack are formed. Gate electrodes are formed between adjacent ones of the insulation layers and surrounding the vertical channel regions. The gate electrodes have a greater thickness at a first location near sidewalls of the insulation layers than at a second location further away from the sidewalls of the insulation layers.Type: ApplicationFiled: November 29, 2012Publication date: May 30, 2013Inventors: Daehong Eom, Kyunghyun Kim, Kwangsu Kim, Jun-Youl Yang, Se-Ho Cha
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Publication number: 20130092872Abstract: Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound. The silicon compound includes a silicon atom, an atomic group having an amino group combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided.Type: ApplicationFiled: August 31, 2012Publication date: April 18, 2013Inventors: Young-Taek Hong, Jinuk Lee, Junghun Lim, Jaewan Park, Chanjin Jeong, Hoon Han, Seonghwan Park, Yanghwa Lee, Sang Won Bae, Daehong Eom, Byoungmoon Yoon, Jihoon Jeong, Kyunghyun Kim, Kyounghwan Kim, ChangSup Mun, Se-Ho Cha, Yongsun Ko
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Patent number: 8404548Abstract: A method of manufacturing a nonvolatile memory device having a three-dimensional memory device includes alternately stacking a plurality of first and second material layers having a different etching selectivity on a semiconductor substrate; forming an opening penetrating the plurality of first and second material layers; removing the first material layers exposed by the opening to form extended portions extending in a direction perpendicular to the semiconductor substrate from the opening; conformally forming a charge storage layer along a surface of the opening and the extended portions; and removing the charge storage layer formed on sidewalls of the second material layers to locally form the charge storage layer patterns in the extended portions.Type: GrantFiled: July 11, 2011Date of Patent: March 26, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Imsoo Park, Young-Hoo Kim, Changki Hong, Jaedong Lee, Daehong Eom, Sung-Jun Kim