Abstract: A pixel structure of a display apparatus includes an electrode line, at least one ultra small light-emitting diode, and a connection electrode. The electrode line includes a second electrode separated from a first electrode and at a same level as the first electrode on a base substrate. The at least one ultra small light-emitting diode is on the base substrate and has a length less than a distance between the first and second electrodes. A connection electrode includes a first contact electrode connecting the first electrode to the ultra small light-emitting diode and a second contact electrode connecting the second electrode to the ultra small light-emitting diode.

Abstract: A protective film includes a first layer having a middle area, a first side area extended from a first edge of the middle area, a second side area extended from a second edge of the middle area intersecting the first edge of the middle area, and a corner area extending from the first side area and the second side area, and a second layer disposed on the first layer and exposing at least a portion of the corner area of the first layer.

Abstract: A multiplexer selects one of a first to a fourth data signal in response to a first to a fourth pulse. The first to fourth pulses respectively correspond to the first to fourth data signals and sequentially toggle. The multiplexer includes: (1) a NAND gate that receives the first data signal, a fourth complementary data signal that is a complementary signal of the fourth data signal, and the first pulse and outputs a first gate signal and (2) a NOR gate that receives the first data signal, the fourth complementary data signal, and a first complementary pulse that is complementary to the first pulse and outputs a second gate signal. The first data signal corresponds to a rising edge of the first pulse, and the fourth complementary data signal corresponds to a rising edge of the fourth pulse.

Abstract: A pixel structure, a display device, and a method of manufacturing a pixel structure, the pixel structure including a base substrate; at least one first electrode arranged in an upper portion of the base substrate; at least one second electrode having a circular shape extending along a circumferential direction around the at least one first electrode; and a plurality of LED elements connected to the first and second electrodes.

Abstract: Methods of fabricating a three-dimensional semiconductor memory device are provided. A method may include forming a mold structure on a substrate including channel regions and a non-channel region between the channel regions, and forming, on the mold structure, a multilayered mask layer including a first mask layer, an etch stop layer, and a second mask layer that are sequentially stacked. The multilayered mask layer may include mask holes exposing the mold structure in the channel regions, dummy mask holes exposing the first mask layer in the non-channel region, and buffer spacers covering sidewalls of the second mask layer exposed by the mask holes and the dummy mask holes. The method may include etching the mold structure using the multilayered mask layer as an etch mask to form channel holes in the channel regions.

Abstract: An example image forming apparatus includes a user interface device, an image forming job operator, a processor, and a memory. The processor executes instructions to display a preview screen of a document through the user interface device, perform an embedding process of embedding user-specific information into a plurality of user-specific information input areas included in the document, display state information of the plurality of user-specific information input areas on the preview screen in synchronization with progress of the embedding process, and, when the embedding process is completed, perform an image forming job with respect to the document in which the user-specific information is embedded, through the image forming job operator.

Abstract: Disclosed are fusion memory devices and methods of fabricating the same. The fusion memory device comprises a first memory device including a first substrate having active and inactive surfaces opposite to each other and a first memory cell circuit on the active surface of the first substrate, a non-memory device including a second substrate having active and inactive surfaces opposite to each other and a non-memory circuit on the active surface of the second substrate, the non-memory device being provided on the first memory device, and a second memory device on the inactive surface of the second substrate and including a second memory cell circuit different from the first memory cell circuit. The non-memory device lies between the first and second memory cell circuits and controls an electrical operation of each of the first and second memory cell circuits.

Abstract: A battery module including a plurality of battery sub packs and an electronic device including the battery module is provided. The battery module comprises a battery pack including a plurality of battery sub packs, a power delivery circuit connectable to the plurality of battery sub packs, a plurality of switches connected between the plurality of battery sub packs and the power delivery circuit, and at least one processor configured to control the plurality of switches to transmit power stored in a first battery sub pack to the power delivery circuit during a first time interval and transmit power stored in the power delivery circuit to a second battery sub pack during a second time interval. Other various embodiments are also provided herein.

Abstract: An electronic apparatus is provided. The electronic apparatus includes a display, a camera configured to capture a rear of the electronic apparatus facing a front of the electronic apparatus in which the display displays an image, and a processor configured to render a virtual object based on the image captured by the camera, based on a user body being detected from the captured image, estimate a plurality of joint coordinates with respect to the detected user body using a pre-trained learning model, generate an augmented reality image using the estimated plurality of joint coordinates, the rendered virtual object, and the captured image, and control the display to display the generated augmented reality image, wherein the processor is configured to identify whether the user body touches the virtual object based on the plurality of estimated joint coordinates, and change a transmittance of the virtual object based on the touch being identified.

Abstract: A semiconductor device includes a peripheral circuit region including a first substrate and circuit elements on the first substrate; and a memory cell region including a second substrate on an upper portion of the first substrate, gate electrodes spaced apart from each other and vertically stacked on the second substrate, channel structures extending vertically through the gate electrodes to the second substrate, first separation regions penetrating through the gate electrodes between the channel structures and extending in one direction, and a second separation region extending vertically to penetrate through the second substrate from above and having a bent portion due to a change in width.

Abstract: A method of operating an image processing apparatus is provided. The method includes generating a first feature map by performing a convolution operation between a first image and a first kernel group, generating a second feature map by performing a convolution operation between the first image and a second kernel group, generating a first combination map based on the first feature map, generating a second combination map based on the first feature map and the second feature map, generating a second image based on the first combination map and the second combination map, and generating a reconstructed image of the first image, based on the second image and the first image, and generating a high-resolution image of the first image by inputting the reconstructed image to an upscaling model.

Abstract: A display device includes a substrate, a first electrode extending in a first direction on the substrate, a first partition wall extending in the first direction on a central portion of the first electrode, a second electrode extending in parallel with the first electrode on the substrate, a second partition wall extending in the first direction on a central portion of the second electrode, and a plurality of light-emitting diodes electrically connected between the first electrode and the second electrode.

Abstract: A semiconductor device includes a first switch coupling a first switch coupling a first power source and a first node according to a first control signal; a sense amplifier coupled between the first node and a second node and performing a sensing operation; a second switch coupling a second power source and the second node according to a second control signal; and a sense amplifier control circuit providing the first control signal and the second control signal. The sense amplifier control circuit controls the second control signal so that a voltage of the second node reaches a shift voltage higher than a voltage of the second power source during a first sensing period of the sensing operation and a bias current flows through the second node during a second sensing period of the sensing operation. The sensing period is subsequent to the first sensing period.

Abstract: A refrigerator of the present disclosure includes an inner case configured to have a storage chamber, a door configured to open and close the storage chamber, a plurality of side panels configured to cover both sides of the inner case, the plurality of side panels being configured to be formed of a metal material, a case supporter configured to support the inner case, a base configured to support a lower side of the case supporter, at least a portion of the base being configured to be spaced apart from a lower side of the door and the case supporter, and a base panel configured to be attached to an upper surface of the base adjacent to the door, the base panel being configured to be formed of the same material as that of the plurality of side panels or having a metal texture.

Abstract: Provided is a separator for a secondary battery including a porous substrate and a coating layer disposed on at least one surface of the porous substrate. The coating layer includes a first fluorine-based binder including a vinylidene fluoride (VDF)-derived unit and a hexafluoropropylene (HFP)-derived unit, and a second fluorine-based binder including vinylidene fluoride (VDF)-derived unit and a tetrafluoroethylene (TFE)-derived unit, the hexafluoropropylene (HFP)-derived unit is included in an amount of less than or equal to 5 mol % based on 100 mol % of the first fluorine-based binder, the tetrafluoroethylene (TFE)-derived unit is included in an amount of greater than 10 mol % and less than or equal to 40 mol % based on 100 mol % of the second fluorine-based binder.

Abstract: Disclosed is a three-dimensional semiconductor memory device comprising intergate dielectric layers and electrode layers alternately stacked on a substrate, a vertical semiconductor pattern that penetrate the intergate dielectric layers and the electrode layers and extends into the substrate, blocking dielectric patterns between the vertical semiconductor pattern and the electrode layers, a tunnel dielectric layer between the blocking dielectric patterns and the vertical semiconductor pattern and in contact with the blocking dielectric patterns and simultaneously with the intergate dielectric layers, and first charge storage patterns between the blocking dielectric patterns and the tunnel dielectric layer. One of the first charge storage patterns is in contact with top and bottom surfaces of one of the blocking dielectric patterns.

Abstract: An apparatus, a memory device, and a method for storing parameter codes with respect to asymmetric on-die-termination (ODT) are provided. The apparatus is connected to an external device via a signal line, and includes: an on-die termination (ODT) circuit set in a first ODT state; a plurality of signal pins, each of which is connected to the signal line; and an ODT control circuit configured to: identify whether a second ODT state of the external device corresponds to the first ODT state, and based on the apparatus being an asymmetric ODT in which the first ODT state and the second ODT state are different, provide an asymmetric ODT parameter code to the external device, and disable the ODT circuit when a signal is not transmitted through the signal line.

Abstract: An integrated circuit device, a semiconductor substrate, and a test system including the integrated circuit device are disclosed. The integrated circuit device includes a power terminal configured to receive a source voltage, a power via connected to the power terminal and passing through at least one of a number of layers, a number of inductive vias arranged apart from the power via and passing through at least one of the number of layers, a number of wirings connected to ends of at least some of the number of inductive vias and configured to form a coil wound in toroidal form together with the number of inductive vias, around the power via, and a test terminal configured to output an induced voltage in the coil externally of the integrated circuit device, in response to the supply of the source voltage.

Abstract: Disclosed are fusion memory devices and methods of fabricating the same. The fusion memory device comprises a first memory device including a first substrate having active and inactive surfaces opposite to each other and a first memory cell circuit on the active surface of the first substrate, a non-memory device including a second substrate having active and inactive surfaces opposite to each other and a non-memory circuit on the active surface of the second substrate, the non-memory device being provided on the first memory device, and a second memory device on the inactive surface of the second substrate and including a second memory cell circuit different from the first memory cell circuit. The non-memory device lies between the first and second memory cell circuits and controls an electrical operation of each of the first and second memory cell circuits.

Abstract: A pixel structure of a display apparatus includes an electrode line, at least one ultra small light-emitting diode, and a connection electrode. The electrode line includes a second electrode separated from a first electrode and at a same level as the first electrode on a base substrate. The at least one ultra small light-emitting diode is on the base substrate and has a length less than a distance between the first and second electrodes. A connection electrode includes a first contact electrode connecting the first electrode to the ultra small light-emitting diode and a second contact electrode connecting the second electrode to the ultra small light-emitting diode.