Patents by Inventor Dae-Hyun KOH

Dae-Hyun KOH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Bit line sense amplifier circuit capable of reducing offset voltage
    Patent number: 10950279
    Abstract: A BLSA circuit includes a first inverter disposed between a first sensing node and a second inner bit line, a second inverter disposed between a second sensing node and a first inner bit line, a first capacitor disposed between a first bit line and the first sensing node, a second capacitor disposed between a second bit line and the second sensing node, a first offset canceling switch for electrically coupling the first inner bit line with the second sensing node during an offset canceling operation, a second offset canceling switch for electrically coupling the second inner bit line with the first sensing node during the offset canceling operation, a first isolation switch for electrically coupling the first bit line with the first inner bit line, and a second isolation switch for electrically coupling the second bit line with the second inner bit line.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: March 16, 2021
    Assignees: SK hynix Inc., Seoul National University R&DB Foundation
    Inventors: Deog-Kyoon Jeong, Jung Min Yoon, Hyungrok Do, Dae-Hyun Koh
  • BIT LINE SENSE AMPLIFIER CIRCUIT
    Publication number: 20200075065
    Abstract: A BLSA circuit includes a first inverter disposed between a first sensing node and a second inner bit line, a second inverter disposed between a second sensing node and a first inner bit line, a first capacitor disposed between a first bit line and the first sensing node, a second capacitor disposed between a second bit line and the second sensing node, a first offset canceling switch for electrically coupling the first inner bit line with the second sensing node during an offset canceling operation, a second offset canceling switch for electrically coupling the second inner bit line with the first sensing node during the offset canceling operation, a first isolation switch for electrically coupling the first bit line with the first inner bit line, and a second isolation switch for electrically coupling the second bit line with the second inner bit line.
    Type: Application
    Filed: August 20, 2019
    Publication date: March 5, 2020
    Inventors: Deog-Kyoon JEONG, Jung Min YOON, Hyungrok DO, Dae-Hyun KOH