Abstract: Disclosed is an inductor device including a first curved metal plate, a second curved metal plate below and substantially vertically aligned with the first curved metal plate, and a first elongated via vertically aligned between the first curved metal plate and the second curved metal plate, the first elongated via configured to conductively couple the first curved metal plate to the second curved metal plate and having an aspect ratio of a width to a height of the first elongated via of at least approximately 2 to 1.

Abstract: A laminate substrate inductor reduces insertion loss and improves isolation while reducing the area for integrating the laminate substrate inductor. The laminate substrate includes a spiral trace. The laminate substrate also includes a first capture pad at a first end of the spiral trace. The first end is located at a corner of the spiral trace. The first capture pad is substantially within a bounding box of the spiral trace. At least a portion of the first capture pad and an outer edge of the spiral trace have a same distance from a ground.

Abstract: A multi-layer spiral inductive array includes a first multi-layer spiral inductor with a second layer matching a spiral pattern of a first layer. The multi-layer spiral inductive array also includes a second multi-layer spiral inductor with a third layer matching a spiral pattern of a fourth layer. The second multi-layer spiral inductor is coupled in series with the first multi-layer spiral inductor.

Abstract: A device includes a glass substrate and a capacitor. The capacitor includes a first metal coupled to a first electrode, a dielectric structure, and a via structure comprising a second electrode of the capacitor. The first metal structure is separated from the via structure by the dielectric structure.

Abstract: Base pads are spaced by a pitch on a support surface. Conducting members, optionally Cu or other metal pillars, extend up from the base pads to top pads. A top pad interconnector connects the top pads in a configuration establishing an inductor current path between the base pads.

Abstract: An exemplary improved ground for a power amplifier circuit may include structural separation of the drive amplifier and the power amplifier grounds and cut-off of the power amplifier induced feedback current to ensure stability under a wide-range of operating conditions. The exemplary power amplifier may include a first ground coupled to a first amplifier circuit, a second ground coupled to a second amplifier circuit separate from the first ground, and the first amplifier circuit generates a drive current for the second amplifier circuit.

Abstract: Disclosed is an apparatus including a plurality of vias each having a defined shape, wherein each of the plurality of vias includes a first two-dimensional conductive layer plated on a first side of a substrate, the first two-dimensional conductive layer having the defined shape, a second two-dimensional conductive layer plated on a second side of the substrate, the second two-dimensional conductive layer having the defined shape, and a via conductively coupling the first two-dimensional conductive layer to the second two-dimensional conductive layer. The apparatus further includes a plurality of interconnects configured to conductively couple the plurality of vias, wherein the first two-dimensional conductive layer and the second two-dimensional conductive layer of each of the plurality of vias are perpendicular to the plurality of interconnects.

Abstract: In exemplary aspects of the disclosure, magnetic coupling problems in a power amplifier/antenna circuit may be address by using a self-shielded RF inductor mounted over the PA output match inductor embedded in the substrate to offer full RF isolation of both PA output match inductors (self-shielded and embedded) or using a self-shielded RF inductor mounted over the PA output match inductor embedded in the substrate along with a component level conformal shield around the self-shielded inductor on the assembly structure.

Abstract: A device includes a passive-on-glass (POG) structure and an interface layer. The POG structure includes a passive component and at least one contact pad on a first surface of a glass substrate. The interface layer has a second surface on the first surface of the glass substrate such that the passive component and the at least one contact pad are located between the first surface of the glass substrate and the interface layer. The interface layer includes at least one land grid array (LGA) pad formed on a third surface of the interface layer, where the third surface of the interface layer is opposite the second surface of the interface layer. The interface layer also includes at least one via formed in the interface layer configured to electrically connect the at least one contact pad with the at least one LGA pad.

Abstract: A method includes forming a first conductive spiral and a second conductive spiral of a spiral inductor coupled to a substrate. The second conductive spiral overlays the first conductive spiral. A first portion of an innermost turn of the spiral inductor has a first thickness in a direction perpendicular to the substrate. The first portion of the innermost turn includes a first portion of the first conductive spiral and does not include the second conductive spiral. A second portion of the innermost turn includes a first portion of the second conductive spiral. A portion of an outermost turn of the spiral inductor has a second thickness in the direction perpendicular to the substrate. The second thickness is greater than the first thickness. The portion of the outermost turn includes a second portion of the first conductive spiral and a second portion of the second conductive spiral.

Abstract: An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.

Abstract: An inductor with multiple loops and semiconductor devices with such an inductor integrated thereon are proposed. In an aspect, the semiconductor device may include a die on a substrate, an inductor on the die in which the inductor comprises a wire with multiple non-planar loops above the die. In another aspect, the semiconductor device may include a plurality of posts on a die on a substrate, and an inductor on the die. The inductor may include a wire looped around the plurality of posts such that the inductor includes multiple non-planar loops.

Abstract: A substrate includes a first dielectric layer, a magnetic core at least partially in the first dielectric layer, where the magnetic core comprises a first non-horizontal thin film magnetic (TFM) layer. The substrate also includes a first inductor that includes a plurality of first interconnects, where the first inductor is positioned in the substrate to at least partially surround the magnetic core. The magnetic core may further include a second non-horizontal thin film magnetic (TFM) layer. The magnetic core may further include a core layer. The magnetic core may further include a third thin film magnetic (TFM) layer, and a fourth thin film magnetic (TFM) layer that is substantially parallel to the third thin film magnetic (TFM) layer.

Abstract: A skewed, co-spiral inductor structure may include a first trace arranged in a first spiral pattern that is supported by a substrate. The skewed, co-spiral inductor structure may also include a second trace arranged in a second spiral pattern, in which the second trace is coupled to the first trace. The first trace may overlap with the second trace in orthogonal overlap areas. In addition, each orthogonal overlap area may have a size defined by a width of the first trace and the width of the second trace. Also, parallel edges of the first trace and the second trace may be arranged to coincide.

Abstract: A stepped-width, co-spiral inductor structure includes a first exterior layer having a first exterior width. The stepped-width, co-spiral inductor structure also includes a first interior layer coupled to the first exterior layer. The first interior layer includes a first interior width that is wider than the first exterior width of the first exterior layer. The stepped-width, co-spiral inductor structure further includes a second exterior layer coupled to the first interior layer. The second exterior layer includes a second exterior width that is narrower than the first interior width of the first interior layer.

Abstract: In conventional device packages, separate standalone inductors are provided and mounted on an interposer substrate along with a die. Separate inductors reduce integration density, decrease flexibility, increase footprint, and generally increase costs. To address such disadvantages, it is proposed to provide a part of an inductor in a substrate below a die. The proposed stacked substrate inductor may include a first inductor in a first substrate, a second inductor in a second a second substrate stacked on the first substrate, and an inductor interconnect coupling the first and second inductors. The core regions of the first and second inductors may overlap with each other at least partially. The proposed stacked substrate inductor may enhance integration density, increase flexibility, decrease footprint, and/or reduce costs.

Abstract: Ground shielding is achieved by a conductor shield having conductive surfaces that immediately surround individual chips within a multichip module or device, such as a multichip module or device with flip-chip (FC) bumps. Intra-module shielding between individual chips within the multichip module or device is achieved by electromagnetic or radio-signal (RF) isolation provided by the surfaces of the conductor shield immediately surrounding each of the chips. The conductor shield is directly connected to one or more grounded conductor portions of a substrate or interposer to ensure reliable grounding.

Abstract: A tunable matching network is disclosed. In a particular example, the matching network includes at least one first inductor in a signal path of the matching network. The matching network includes at least one second inductor outside of the signal path. The matching network includes one or more switches coupled to the at least one second inductor. The one or more switches are configured to selectively enable mutual coupling of the at least one first inductor and the at least one second inductor.

Abstract: An exemplary improved ground for a power amplifier circuit may include structural separation of the drive amplifier and the power amplifier grounds and cut-off of the power amplifier induced feedback current to ensure stability under a wide-range of operating conditions. The exemplary power amplifier may include a first ground coupled to a first amplifier circuit, a second ground coupled to a second amplifier circuit separate from the first ground, and the first amplifier circuit generates a drive current for the second amplifier circuit.

Abstract: A multi-layer spiral inductive array includes a first multi-layer spiral inductor with a second layer matching a spiral pattern of a first layer. The multi-layer spiral inductive array also includes a second multi-layer spiral inductor with a third layer matching a spiral pattern of a fourth layer. The second multi-layer spiral inductor is coupled in series with the first multi-layer spiral inductor.