Abstract: An integrated circuit device includes a substrate having an active region, a word line extending in the substrate in a first horizontal direction, a bit line extending on the word line in a second horizontal direction, a bit line contact electrically connecting the bit line to the active region, a doping contact connecting the bit line contact to the active region, a cell pad having a horizontal width greater than that of the active region, a buried contact that digs into one side wall of the cell pad, and a conductive landing pad facing the bit line in the first horizontal direction. The doping contact includes a first doping contact and a second doping contact, and a thickness of the first doping contact in the vertical direction is less than that of the second doping contact in the vertical direction.

Abstract: A semiconductor device may include a substrate including an active pattern, a conductive filling pattern on an impurity region at an upper portion of the active pattern, a first spacer and a second spacer stacked on a sidewall of the conductive filling pattern in a horizontal direction, and a bit line structure on the conductive filling pattern. The impurity region may include impurities. The horizontal direction may be parallel to an upper surface of the substrate. The first spacer may include an insulating material containing the impurities.

Abstract: A semiconductor memory device includes a substrate, an isolation insulating layer arranged on the substrate, a plurality of word lines arranged on the substrate to extend in a first horizontal direction and to be apart from one another in a vertical direction, a bit line extending in the vertical direction on the isolation insulating layer, a plurality of semiconductor patterns extending from the bit line in a second horizontal direction orthogonal to the first horizontal direction and apart from one another in the vertical direction, and a plurality of information storage elements connected to the plurality of semiconductor patterns. Each of the plurality of semiconductor patterns includes a source region including the same impurity as the isolation insulating layer, a drain region, and a channel region between the source region and the drain region.

Abstract: A semiconductor device includes a substrate, a bit line extending in a first direction on the substrate, a first vertical channel pattern and a second vertical channel pattern on the bit line, a back gate electrode between the first vertical channel pattern and the second vertical channel pattern and extending in a second direction perpendicular to the first direction across the bit line, a first word line extending in the second direction from one side of the first vertical channel pattern, a second word line extending in the second direction from other side of the second vertical channel pattern, and a contact pattern connected to each of the first vertical channel pattern and the second vertical channel pattern. When viewed from a cross-sectional view, each of the first vertical channel pattern and the second vertical channel pattern have a trapezoidal shape with the long sides facing each other.

Abstract: An integrated circuit device includes a substrate having an active region, a word line extending in the substrate in a first horizontal direction, a bit line extending on the word line in a second horizontal direction, a bit line contact electrically connecting the bit line to the active region, a doping contact connecting the bit line contact to the active region, a cell pad having a horizontal width greater than that of the active region, a buried contact that digs into one side wall of the cell pad, and a conductive landing pad facing the bit line in the first horizontal direction. The doping contact includes a first doping contact and a second doping contact, and a thickness of the first doping contact in the vertical direction is less than that of the second doping contact in the vertical direction.

Abstract: A semiconductor device may include a substrate including an active pattern, a conductive filling pattern on an impurity region at an upper portion of the active pattern, a first spacer and a second spacer stacked on a sidewall of the conductive filling pattern in a horizontal direction, and a bit line structure on the conductive filling pattern. The impurity region may include impurities. The horizontal direction may be parallel to an upper surface of the substrate. The first spacer may include an insulating material containing the impurities.