Abstract: Provided is a method for transmitting data. The method includes: transmitting equalization matching data to a source driver chip upon sending a link stable pattern to the source driver chip, wherein the equalization matching data is configured for the source driver chip to determine a target equalization gain, and perform gain compensation, based on the target equalization gain, on display data from the timing controller; and transmitting the display data to the source driver chip in response to a first condition being met, wherein the first condition is that the source driver chip determines the target equalization gain. Prior to transmitting the equalization matching data to the source driver chip upon sending the link stable pattern to the source driver chip, the method further includes transmitting equalization gain configuration information to the source driver chip.

Abstract: A drive control method applicable to a timing controller and a drive circuit are provided. The timing controller includes: M signal output terminals, wherein the M signal output terminals are respectively connected to M signal input terminals corresponding to M source driver chips; the timing controller includes a controller, a timing transmission circuit, and a pull-down circuit. The controller is configured to control the timing transmission circuit and the pull-down circuit, such that the M signal output terminals are connected to ground in a first phase, the M source driver chips are in a low power consumption mode in the case that the M signal input terminals are connected to ground, and the first phase indicates a phase in which the M source driver chips are expected to enter the low power consumption mode.

Abstract: Provided is a method for transmitting data. The method includes: transmitting equalization matching data to a source driver chip upon sending a link stable pattern to the source driver chip, wherein the equalization matching data is configured for the source driver chip to determine a target equalization gain, and perform gain compensation, based on the target equalization gain, on display data from the timing controller; and transmitting the display data to the source driver chip in response to a first condition being met, wherein the first condition is that the source driver chip determines the target equalization gain. Prior to transmitting the equalization matching data to the source driver chip upon sending the link stable pattern to the source driver chip, the method further includes transmitting equalization gain configuration information to the source driver chip.

Abstract: A drive control method applicable to a timing controller and a drive circuit are provided. The timing controller includes: M signal output terminals, wherein the M signal output terminals are respectively connected to M signal input terminals corresponding to M source driver chips; the timing controller includes a controller, a timing transmission circuit, and a pull-down circuit. The controller is configured to control the timing transmission circuit and the pull-down circuit, such that the M signal output terminals are connected to ground in a first phase, the M source driver chips are in a low power consumption mode in the case that the M signal input terminals are connected to ground, and the first phase indicates a phase in which the M source driver chips are expected to enter the low power consumption mode.

Abstract: Provided is a method for transmitting data. The method includes: transmitting equalization matching data to a source driver chip upon sending a link stable pattern to the source driver chip, wherein the equalization matching data is configured for the source driver chip to determine a target equalization gain, and perform gain compensation, based on the target equalization gain, on display data from the timing controller; and transmitting the display data to the source driver chip in response to a first condition being met, wherein the first condition is that the source driver chip determines the target equalization gain.

Abstract: Provided is a timing controller. The timing controller includes: M signal output terminals, wherein the M signal output terminals are respectively connected to M signal input terminals corresponding to M source driver chips; the timing controller includes a controller, a timing transmission circuit, and a pull-down circuit. The controller is configured to control the timing transmission circuit and the pull-down circuit, such that the M signal output terminals are connected to ground in a first phase, the M source driver chips are in a low power consumption mode in the case that the M signal input terminals are connected to ground, and the first phase indicates a phase in which the M source driver chips are expected to enter the low power consumption mode.

Abstract: Provided is a data transmission method, including: sending clock calibration data to a source driver chip, wherein the clock calibration data instructs the source driver chip to perform clock calibration; sending first configuration information to the source driver chip over a data channel in response to completing the clock calibration by the source driver chip, wherein the first configuration information instructs the source driver chip to perform a configuration on a physical layer parameter; and successively sending a link stable pattern and display data to the source driver chip.

Abstract: Provided is a data transmission method in a timing controller. The data transmission method includes sending clock calibration data to a source driver chip, wherein the clock calibration data instructs the source driver chip to perform a clock calibration; successively sending, in response to completing the clock calibration by the source driver chip, a first identification code and an initialization control instruction to the source driver chip over a data channel, wherein the first identification code indicates a start of transmission of the initialization control instruction, and the initialization control instruction comprises configuration information, the configuration information instructing the source driver chip to perform a configuration on a physical layer parameter; and successively sending a link stable pattern and display data to the source driver chip.

Abstract: Provided is a data transmission method in a timing controller. The data transmission method includes sending clock calibration data to a source driver chip, wherein the clock calibration data instructs the source driver chip to perform a clock calibration; successively sending, in response to completing the clock calibration by the source driver chip, a first identification code and an initialization control instruction to the source driver chip over a data channel, wherein the first identification code indicates a start of transmission of the initialization control instruction, and the initialization control instruction comprises configuration information, the configuration information instructing the source driver chip to perform a configuration on a physical layer parameter; and successively sending a link stable pattern and display data to the source driver chip.

Abstract: Provided is a timing controller. The timing controller includes: M signal output terminals, wherein the M signal output terminals are respectively connected to M signal input terminals corresponding to M source driver chips; the timing controller includes a controller, a timing transmission circuit, and a pull-down circuit. The controller is configured to control the timing transmission circuit and the pull-down circuit, such that the M signal output terminals are connected to ground in a first phase, the M source driver chips are in a low power consumption mode in the case that the M signal input terminals are connected to ground, and the first phase indicates a phase in which the M source driver chips are expected to enter the low power consumption mode.

Abstract: Provided is a method for transmitting data. The method includes: transmitting equalization matching data to a source driver chip upon sending a link stable pattern to the source driver chip, wherein the equalization matching data is configured for the source driver chip to determine a target equalization gain, and perform gain compensation, based on the target equalization gain, on display data from the timing controller; and transmitting the display data to the source driver chip in response to a first condition being met, wherein the first condition is that the source driver chip determines the target equalization gain.

Abstract: Provided is a data transmission method, including: sending clock calibration data to a source driver chip, wherein the clock calibration data instructs the source driver chip to perform clock calibration; sending first configuration information to the source driver chip over a data channel in response to completing the clock calibration by the source driver chip, wherein the first configuration information instructs the source driver chip to perform a configuration on a physical layer parameter; and successively sending a link stable pattern and display data to the source driver chip.