Patents by Inventor Daeseon Jeon

Daeseon Jeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and method of manufacturing the same
    Patent number: 11387144
    Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises providing a layout comprising a first group that includes first and second patterns and a second group that includes third and fourth patterns, examining a bridge risk region in the layout, biasing one end of at least one of the first and third patterns, and forming first to fourth conductive patterns by respectively using the first to fourth patterns of the layout. The one end of at least one of the first and third patterns are adjacent to the bridge risk region.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: July 12, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Daeho Yoon, Daeseon Jeon, Jaeyoung Choi
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20210050257
    Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises providing a layout comprising a first group that includes first and second patterns and a second group that includes third and fourth patterns, examining a bridge risk region in the layout, biasing one end of at least one of the first and third patterns, and forming first to fourth conductive patterns by respectively using the first to fourth patterns of the layout. The one end of at least one of the first and third patterns are adjacent to the bridge risk region.
    Type: Application
    Filed: October 14, 2020
    Publication date: February 18, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Daeho YOON, Daeseon JEON, Jaeyoung CHOI
  • Semiconductor device and method of manufacturing the same
    Patent number: 10872817
    Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises providing a layout comprising a first group that includes first and second patterns and a second group that includes third and fourth patterns, examining a bridge risk region in the layout, biasing one end of at least one of the first and third patterns, and forming first to fourth conductive patterns by respectively using the first to fourth patterns of the layout. The one end of at least one of the first and third patterns are adjacent to the bridge risk region.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 22, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Daeho Yoon, Daeseon Jeon, Jaeyoung Choi
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20190172824
    Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises providing a layout comprising a first group that includes first and second patterns and a second group that includes third and fourth patterns, examining a bridge risk region in the layout, biasing one end of at least one of the first and third patterns, and forming first to fourth conductive patterns by respectively using the first to fourth patterns of the layout. The one end of at least one of the first and third patterns are adjacent to the bridge risk region.
    Type: Application
    Filed: June 29, 2018
    Publication date: June 6, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Daeho YOON, Daeseon Jeon, Jaeyoung Choi