Patents by Inventor Dae-Son Kim

Dae-Son Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11963426
    Abstract: A display device includes a sensor having a detection electrode. An optical pattern layer is disposed directly on the sensor and includes a plurality of transmission portions and a light blocking portion. A display panel is disposed on the optical pattern layer. A minimum distance between the detection electrode and the light blocking portion is in a range of 1 micrometer-5 micrometers.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: April 16, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Dae-Young Lee, Gee-Bum Kim, Byung Han Yoo, Sangwoo Kim, Jungha Son, Taekyung Ahn, Yunjong Yeo, Kijune Lee, Jaeik Lim, Min Oh Choi, Chaungi Choi
  • Patent number: 10833706
    Abstract: A method of encoding input data as a polar code includes generating unfrozen bits by adding at least one designated information bit to information bits which have been generated based on the input data, reordering the unfrozen bits and frozen bits by assigning the unfrozen bits to polarized sub-channels having higher reliability than the frozen bits having a value known to both of an encoder and a decoder, and generating a code word by polar-coding results of the reordering may be provided. The at least one designated information bit may have the value known to both the encoder and the decoder.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: November 10, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-son Kim, Min-goo Kim, Se-hyoung Kim
  • Patent number: 10666290
    Abstract: A device for decoding input data including first candidate data and second candidate data by using a polar code, the device includes a first path metric processor configured to generate first candidate path metrics based on a first parent path metric by decoding the first candidate data, determine at least one first child path metric among the first candidate path metrics based on first reliability values of the first candidate path metrics; and a second path metric processor configured to generate second candidate path metrics based on a second parent path metric by decoding the second candidate data, and determine at least one second child path metric among the second candidate path metrics based on second reliability values of the second candidate path metrics, a quantity of the at least one first child path metric being different from a quantity of the at least one second child path metric.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: May 26, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Dae-son Kim
  • Publication number: 20200127680
    Abstract: A device for decoding input data including first candidate data and second candidate data by using a polar code, the device includes a first path metric processor configured to generate first candidate path metrics based on a first parent path metric by decoding the first candidate data, determine at least one first child path metric among the first candidate path metrics based on first reliability values of the first candidate path metrics; and a second path metric processor configured to generate second candidate path metrics based on a second parent path metric by decoding the second candidate data, and determine at least one second child path metric among the second candidate path metrics based on second reliability values of the second candidate path metrics, a quantity of the at least one first child path metric being different from a quantity of the at least one second child path metric.
    Type: Application
    Filed: July 8, 2019
    Publication date: April 23, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Dae-son KIM
  • Publication number: 20180358985
    Abstract: A method of encoding input data as a polar code includes generating unfrozen bits by adding at least one designated information bit to information bits which have been generated based on the input data, reordering the unfrozen bits and frozen bits by assigning the unfrozen bits to polarized sub-channels having higher reliability than the frozen bits having a value known to both of an encoder and a decoder, and generating a code word by polar-coding results of the reordering may be provided. The at least one designated information bit may have the value known to both the encoder and the decoder.
    Type: Application
    Filed: June 6, 2018
    Publication date: December 13, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dae-son KIM, Min-goo KIM, Se-hyoung KIM
  • Patent number: 8201030
    Abstract: A method and apparatus for parallel structured Latin square interleaving in a communication system are provided. The method includes dividing input information bits into sub-blocks according to a parallel processing order, generating a first Latin square matrix or a second Latin square matrix by comparing the parallel processing order with a predetermined threshold, and interleaving by reading out the information bits divided into the sub-blocks according to the generated Latin square matrix.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: June 12, 2012
    Assignees: Samsung Electronics Co., Ltd., Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Seul-Ki Bae, Seung-Hee Han, Jong-Hyeuk Lee, Hong-Yeop Song, Dae-Son Kim, Joon-Sung Kim
  • Publication number: 20090113271
    Abstract: A method and apparatus for parallel structured Latin square interleaving in a communication system are provided. The method includes dividing input information bits into sub-blocks according to a parallel processing order, generating a first Latin square matrix or a second Latin square matrix by comparing the parallel processing order with a predetermined threshold, and interleaving by reading out the information bits divided into the sub-blocks according to the generated Latin square matrix.
    Type: Application
    Filed: October 30, 2008
    Publication date: April 30, 2009
    Applicants: SAMSUNG ELECTRONICS CO., LTD., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Seul-Ki Bae, Seung-Hee Han, Jong-Hyeuk Lee, Hong-Yeop Song, Dae-Son Kim, Joon-Sung Kim
  • Publication number: 20080109618
    Abstract: Provided is a parallel interleaving method and apparatus. The parallel interleaving method includes dividing input information bits into a predetermined number of sub-blocks and interleaving the information bits divided into the sub-blocks according to a predetermined first interleaving rule.
    Type: Application
    Filed: November 7, 2007
    Publication date: May 8, 2008
    Applicants: SAMSUNG ELECTRONICS CO. , LTD., Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Dong-Ho Kim, Yung-Soo Kim, Cheol-Woo You, Hong-Yeop Song, Dae-Son Kim, Hyun-Young Oh