Patents by Inventor Daewon Yang
Daewon Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250046587Abstract: The present disclosure relates to plasma diagnostic devices. An example plasma diagnostic device includes a pinhole through which a first optical signal passes, an optical device in which the first optical signal is incident and the first optical signal is converted into a second optical signal, a filter configured to filter the second optical signal and to output a third optical signal of a specific wavelength band, and a sensor configured to monitor a distribution of the first optical signal, the second optical signal, and the third optical signal.Type: ApplicationFiled: April 15, 2024Publication date: February 6, 2025Inventors: Taehyun Kim, Chansoo Kang, Minju Kim, Daewon Kang, Dougyong Sung, Jungmo Yang, Sejin Oh
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Publication number: 20170170048Abstract: A wafer handler includes a substrate having a front surface and a back surface, an antireflective layer formed over the back surface, a silicon nitride compensation layer formed over the front surface, and a release layer formed over the compensation layer. The wafer handler can be bonded to a device wafer for processing of the device wafer, and debonded from the device wafer using infrared radiation without damaging the device wafer or devices formed thereon.Type: ApplicationFiled: December 9, 2015Publication date: June 15, 2017Applicant: GLOBALFOUNDRIES INC.Inventors: Thuy Tran-Quinn, Daewon Yang, Matthew S. Angyal, Dennis M. Sheehan
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Patent number: 9318344Abstract: A simple, effective and economical method to improved the yield of CMOS devices using contact etching stopper liner, including, single neutral stressed liner, single stressed liner and dual stress liner (DSL), technology is provided. In order to improve the chip yield, the present invention provides a method in which a sputter etching process is employed to smooth/flatten (i.e., thin) the top surface of the contact etch stopper liners. When DSL technology is used, the inventive sputter etching process is used to reduce the complexity caused by DSL boundaries to smooth/flatten top surface of the DSL, which results in significant yield increase. The present invention also provides a semiconductor structure including at least one etched liner.Type: GrantFiled: December 1, 2014Date of Patent: April 19, 2016Assignee: International Business Machines CorporationInventors: Huilong Zhu, Daewon Yang
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Patent number: 9080239Abstract: Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.Type: GrantFiled: March 30, 2012Date of Patent: July 14, 2015Assignee: International Business Machines CorporationInventors: Daewon Yang, Kangguo Cheng, Pavel Smetana, Richard S. Wise, Keith Kwong Hon Wong
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Patent number: 9016236Abstract: A high-density plasma chemical vapor deposition tool and the method for use of the tool is disclosed. The chemical vapor deposition tool allows for angular adjustment of the pedestal that holds the substrate being manufactured. Electromagnets serve as an “electron filter” that allows for angular deposition of material onto the substrate. Methods for fabrication of trench structures and asymmetrical spacers in a semiconductor manufacturing process are also disclosed. The angular deposition saves process steps, thereby reducing time, complexity, and cost of manufacture, while improving overall product yield.Type: GrantFiled: August 4, 2008Date of Patent: April 28, 2015Assignee: International Business Machines CorporationInventors: Daewon Yang, Kangguo Cheng, Pavel Smetana, Richard S. Wise, Keith Kwong Hon Wong
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Publication number: 20150087121Abstract: A simple, effective and economical method to improved the yield of CMOS devices using contact etching stopper liner, including, single neutral stressed liner, single stressed liner and dual stress liner (DSL), technology is provided. In order to improve the chip yield, the present invention provides a method in which a sputter etching process is employed to smooth/flatten (i.e., thin) the top surface of the contact etch stopper liners. When DSL technology is used, the inventive sputter etching process is used to reduce the complexity caused by DSL boundaries to smooth/flatten top surface of the DSL, which results in significant yield increase. The present invention also provides a semiconductor structure including at least one etched liner.Type: ApplicationFiled: December 1, 2014Publication date: March 26, 2015Inventors: Huilong Zhu, Daewon Yang
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Publication number: 20140302685Abstract: A dielectric cap and related methods are disclosed. In one embodiment, the dielectric cap includes a dielectric material having an optical band gap (e.g., greater than about 3.0 electron-Volts) to substantially block ultraviolet radiation during a curing treatment, and including nitrogen with electron donor, double bond electrons. The dielectric cap exhibits a high modulus and is stable under post ULK UV curing treatments for, for example, copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability.Type: ApplicationFiled: June 18, 2014Publication date: October 9, 2014Inventors: Michael P. Belyansky, Griselda Bonilla, Xiao Hu Liu, Son V. Nguyen, Thomas M. Shaw, Hosadurga K. Shobha, Daewon Yang
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Patent number: 8679938Abstract: A method for formation of a shallow trench isolation (STI) in an active region of a device comprising trench capacitive elements, the trench capacitive elements comprising a metal plate and a high-k dielectric includes etching a STI trench in the active region of the device, wherein the STI trench is directly adjacent to at least one of the metal plate or high-k dielectric of the trench capacitive elements; and forming an oxide liner in the STI trench, wherein the oxide liner is formed selectively to the metal plate or high-k dielectric, wherein forming the oxide liner is performed at a temperature of about 600° C. or less.Type: GrantFiled: February 6, 2012Date of Patent: March 25, 2014Assignee: International Business Machines CorporationInventors: Sunfei Fang, Oleg Gluschenkov, Byeong Y. Kim, Rishikesh Krishnan, Daewon Yang
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Patent number: 8557649Abstract: Methods for controlling the height of semiconductor structures are disclosed. Amorphous carbon is used as a stopping layer for controlling height variability. In one embodiment, the height of replacement metal gates for transistors is controlled. In another embodiment, the step height of a shallow trench isolation region is controlled.Type: GrantFiled: October 21, 2011Date of Patent: October 15, 2013Assignee: International Business Machines CorporationInventors: Rajasekhar Venigalla, Michael Vincent Aquilino, Massud A. Aminpur, Michael P. Belyansky, Unoh Kwon, Christopher Duncan Sheraw, Daewon Yang
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Publication number: 20130200482Abstract: A method for formation of a shallow trench isolation (STI) in an active region of a device comprising trench capacitive elements, the trench capacitive elements comprising a metal plate and a high-k dielectric includes etching a STI trench in the active region of the device, wherein the STI trench is directly adjacent to at least one of the metal plate or high-k dielectric of the trench capacitive elements; and forming an oxide liner in the STI trench, wherein the oxide liner is formed selectively to the metal plate or high-k dielectric, wherein forming the oxide liner is performed at a temperature of about 600° C. or less.Type: ApplicationFiled: February 6, 2012Publication date: August 8, 2013Applicant: International Business Machines CorporationInventors: Sunfei FANG, Oleg GLUSCHENKOV, Byeong Y. KIM, Rishikesh KRISHNAN, Daewon YANG
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Publication number: 20130102125Abstract: Methods for controlling the height of semiconductor structures are disclosed. Amorphous carbon is used as a stopping layer for controlling height variability. In one embodiment, the height of replacement metal gates for transistors is controlled. In another embodiment, the step height of a shallow trench isolation region is controlled.Type: ApplicationFiled: October 21, 2011Publication date: April 25, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Rajasekhar Venigalla, Michael Vincent Aquilino, Massud A. Aminpur, Michael P. Belyansky, Unoh Kwon, Christopher Duncan Sheraw, Daewon Yang
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Publication number: 20120190203Abstract: Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.Type: ApplicationFiled: March 30, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daewon Yang, Kangguo Cheng, Pavel Smetana, Richard S. Wise, Keith Kwong Hon Wong
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Publication number: 20120027956Abstract: A method of forming a nitride film is disclosed. In one embodiment, the method comprises performing an ending film deposition process that differs from the main film deposition process in terms of the flow rates of the reactive and ion source gases, and maintaining acceleration power of a CVD tool during the ending film deposition process. A post deposition process may also be used to remove a denser top layer of nitride, resulting in a nitride film having a consistent density.Type: ApplicationFiled: July 29, 2010Publication date: February 2, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daewon Yang, Anthony Gene Domenicucci, Aurelia Suwarno-Handayana, Shamas Musthafa Ummer
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Patent number: 8030707Abstract: A method of forming a silicon-on-insulator (SOI) semiconductor structure in a substrate having a bulk semiconductor layer, a buried oxide (BOX) layer and an SOI layer. During the formation of a trench in the structure, the BOX layer is undercut. The method includes forming a dielectric material on the upper wall of the trench adjacent to the undercutting of the BOX layer and then etching the dielectric material to form a spacer. The spacer fixes the BOX layer undercut and protects it during subsequent steps of forming a bottle-shaped portion of the trench, forming a buried plate in the deep trench; and then forming a trench capacitor. There is also a semiconductor structure, preferably an SOI eDRAM structure, having a spacer which fixes the undercutting in the BOX layer.Type: GrantFiled: February 23, 2009Date of Patent: October 4, 2011Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Naftali Eliahu Lustig, Daewon Yang
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Patent number: 7943467Abstract: A method of producing a semiconducting device is provided that in one embodiment includes providing a semiconducting device including a gate structure atop a substrate, the gate structure including a dual gate conductor including an upper gate conductor and a lower gate conductor, wherein at least the lower gate conductor includes a silicon containing material; removing the upper gate conductor selective to the lower gate conductor; depositing a metal on at least the lower gate conductor; and producing a silicide from the metal and the lower gate conductor. In another embodiment, the inventive method includes a metal as the lower gate conductor.Type: GrantFiled: January 18, 2008Date of Patent: May 17, 2011Assignee: International Business Machines CorporationInventors: Huilong Zhu, Brian J. Greene, Yanfeng Wang, Daewon Yang
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Patent number: 7851376Abstract: Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cm2 and 5.0 W/cm2; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.Type: GrantFiled: February 2, 2009Date of Patent: December 14, 2010Assignee: International Business Machines CorporationInventors: Daewon Yang, Woo-Hyeong Lee, Tai-chi Su, Yun-Yu Wang
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Patent number: 7804136Abstract: A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 ?.Type: GrantFiled: October 19, 2007Date of Patent: September 28, 2010Assignee: International Business Machines CorporationInventors: Richard A. Conti, Ronald P. Bourque, Nancy R. Klymko, Anita Madan, Michael C. Smits, Roy H. Tilghman, Kwong Hon Wong, Daewon Yang
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Publication number: 20100213522Abstract: A method of forming a silicon-on-insulator (SOI) semiconductor structure in a substrate having a bulk semiconductor layer, a buried oxide (BOX) layer and an SOI layer. During the formation of a trench in the structure, the BOX layer is undercut. The method includes forming a dielectric material on the upper wall of the trench adjacent to the undercutting of the BOX layer and then etching the dielectric material to form a spacer. The spacer fixes the BOX layer undercut and protects it during subsequent steps of forming a bottle-shaped portion of the trench, forming a buried plate in the deep trench; and then forming a trench capacitor. There is also a semiconductor structure, preferably an SOI eDRAM structure, having a spacer which fixes the undercutting in the BOX layer.Type: ApplicationFiled: February 23, 2009Publication date: August 26, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Naftali Eliahu Lustig, Daewon Yang
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Patent number: 7750414Abstract: A structure comprises at least one transistor on a substrate, an insulator layer over the transistor, and an ion stopping layer over the insulator layer. The ion stopping layer comprises a portion of the insulator layer that is damaged and has either argon ion damage or nitrogen ion damage.Type: GrantFiled: May 29, 2008Date of Patent: July 6, 2010Assignee: International Business Machines CorporationInventors: Huilong Zhu, Yanfeng Wang, Daewon Yang, Huajie Chen
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Publication number: 20100029082Abstract: Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.Type: ApplicationFiled: August 4, 2008Publication date: February 4, 2010Applicant: International Business Machines CorporationInventors: Daewon Yang, Kangguo Cheng, Pavel Smetana, Richard S. Wise, Keith Kwong Hon Wong