Abstract: An operating method of a storage device includes transmitting, by a storage controller, data and the transmission parity data to the non-volatile memory with respect to each data line, performing a counting operation, by a non-volatile memory, to count a number of transmission error bits with respect to each data line in a first group, based on first transmission parity data, performing a determination operation, by the non-volatile memory, to determine whether there is a transmission error with respect to each data line in a second group, based on second transmission parity data, determining, by the non-volatile memory, whether a condition for performing retraining is satisfied, based on a counting result generated from the counting operation and a determination result generated from the determination operation, and transmitting, by the non-volatile memory, transmission error status information to the storage controller when the condition for performing retraining is satisfied.

Abstract: An LDPC encoder is described with memory for storing a parity check matrix and a calculation unit to encode information bits into a codeword with reference to the parity check matrix. The parity check matrix includes an information part matrix and a parity part matrix. In the parity part matrix, Z*Z sub-matrices are sub-matrices, other than a zero matrix, and are arranged in each of the m rows and m columns. A sub-matrix is a scaled cyclic matrix obtained by shifting elements of an identity matrix by one to the left and multiplying the shifted elements by a scaling element. Except for the scaled cyclic matrix, the remaining sub-matrices are a zero matrix or an identity matrix, and the scaling element is an element allowing the parity part matrix to satisfy a full rank condition on a Galois field.

Abstract: An LDPC encoder is described with memory for storing a parity check matrix and a calculation unit to encode information bits into a codeword with reference to the parity check matrix. The parity check matrix includes an information part matrix and a parity part matrix. In the parity part matrix, Z*Z sub-matrices are sub-matrices, other than a zero matrix, and are arranged in each of the m rows and m columns. A sub-matrix is a scaled cyclic matrix obtained by shifting elements of an identity matrix by one to the left and multiplying the shifted elements by a scaling element. Except for the scaled cyclic matrix, the remaining sub-matrices are a zero matrix or an identity matrix, and the scaling element is an element allowing the parity part matrix to satisfy a full rank condition on a Galois field.

Abstract: A generalized low-density parity-check (G-LDPC) encoder, including a plurality of generalized constraint (GC) encoders configured to perform a plurality of GC encoding operations in parallel based on a GC code having a quasi-cyclic (QC) structure including information variable nodes, inner parity variable nodes, and super check nodes configured to perform multiple condition checks, wherein each GC encoder of the plurality of GC encoders includes a plurality of first logic circuits configured to perform a GC encoding operation of the plurality of GC encoding operations; and an LDPC encoder configured to perform an LDPC encoding operation based on an LDPC code having the QC structure, wherein the LDPC encoder includes a plurality of single check nodes configured to perform a single parity check, wherein the each GC encoder is configured to receive information bits, and to determine parity bits of a portion of inner parity bits corresponding to the information bits by enabling only a portion of the plurality of

Abstract: An LDPC encoder is described with memory for storing a parity check matrix and a calculation unit to encode information bits into a codeword with reference to the parity check matrix. The parity check matrix includes an information part matrix and a parity part matrix. In the parity part matrix, Z*Z sub-matrices are sub-matrices, other than a zero matrix, and are arranged in each of the m rows and m columns. A sub-matrix is a scaled cyclic matrix obtained by shifting elements of an identity matrix by one to the left and multiplying the shifted elements by a scaling element. Except for the scaled cyclic matrix, the remaining sub-matrices are a zero matrix or an identity matrix, and the scaling element is an element allowing the parity part matrix to satisfy a full rank condition on a Galois field.

Abstract: A decoding device and a decoding method which relate to: receiving a codeword; estimating a number of errors included in the received codeword; and decoding the codeword based on the estimated number of errors using at least one of a first parity check matrix and a second parity check matrix, wherein the first parity check matrix corresponds to a first low-density parity check (LDPC) code, and the second parity check matrix corresponds to a second LDPC code, and wherein the first parity check matrix is based on a first code type, and the second parity check matrix is based on a second code type different from the first code type.

Abstract: A generalized low-density parity-check (G-LDPC) encoder, including a plurality of generalized constraint (GC) encoders configured to perform a plurality of GC encoding operations in parallel based on a GC code having a quasi-cyclic (QC) structure including information variable nodes, inner parity variable nodes, and super check nodes configured to perform multiple condition checks, wherein each GC encoder of the plurality of GC encoders includes a plurality of first logic circuits configured to perform a GC encoding operation of the plurality of GC encoding operations; and an LDPC encoder configured to perform an LDPC encoding operation based on an LDPC code having the QC structure, wherein the LDPC encoder includes a plurality of single check nodes configured to perform a single parity check, wherein the each GC encoder is configured to receive information bits, and to determine parity bits of a portion of inner parity bits corresponding to the information bits by enabling only a portion of the plurality of

Abstract: A method and a device for transmitting a signal by using a polar code are provided. The method includes generating a first codeword by applying the polar code to an input signal, dividing the first codeword into a plurality of partial vectors, allocating a shaping bit to the input signal when at least one of the plurality of partial vectors does not satisfy a preset Hamming weight condition, generating a second codeword by applying the polar code to the input signal to which the shaping bit is allocated, and transmitting a signal based on the second codeword.

Abstract: The present disclosure relates to a pre-5t-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). A method for operating a transmitting stage in a wireless communication system includes generating a signal by encoding an input bit sequence according to polar code determined from a linear code, and transmitting the signal to a receiving stage. The input bit sequence includes a second frozen bit which is determined based on a first frozen bit and an information bit. The first frozen bit and the information bit precede the second frozen bit in the input bit sequence.

Abstract: A communication scheme and system for converging a 5th generation (5G) communication system for supporting a data rate higher than that of a 4th generation (4G) system with an internet of things (IoT) technology are provided. The present disclosure is applicable to intelligent services (e.g., smart home, smart building, smart city, smart car or connected car, health care, digital education, retail, and security and safety-related services) based on the 5G communication technology and the IoT-related technology. The disclosure relates to a punctured polar code design method and apparatus and proposes optimal puncturing pattern and information set selection criteria for designing punctured polar codes.

Abstract: The present disclosure relates to a pre-5t-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). A method for operating a transmitting stage in a wireless communication system includes generating a signal by encoding an input bit sequence according to polar code determined from a linear code, and transmitting the signal to a receiving stage. The input bit sequence includes a second frozen bit which is determined based on a first frozen bit and an information bit. The first frozen bit and the information bit precede the second frozen bit in the input bit sequence.

Abstract: A method and a device for transmitting a signal by using a polar code are provided. The method includes generating a first codeword by applying the polar code to an input signal, dividing the first codeword into a plurality of partial vectors, allocating a shaping bit to the input signal when at least one of the plurality of partial vectors does not satisfy a preset Hamming weight condition, generating a second codeword by applying the polar code to the input signal to which the shaping bit is allocated, and transmitting a signal based on the second codeword.

Abstract: A communication scheme and system for converging a 5th generation (5G) communication system for supporting a data rate higher than that of a 4th generation (4G) system with an internet of things (IoT) technology are provided. The present disclosure is applicable to intelligent services (e.g., smart home, smart building, smart city, smart car or connected car, health care, digital education, retail, and security and safety-related services) based on the 5G communication technology and the IoT-related technology. The disclosure relates to a punctured polar code design method and apparatus and proposes optimal puncturing pattern and information set selection criteria for designing punctured polar codes.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system for supporting higher data rates Beyond 4th-Generation (4G) communication systems such as Long Term Evolution (LTE). A method for operating a receiver in a wireless communication system may include: receiving a signal from a transmitter; performing Integer Forcing (IF) equalization on the received signal; determining a log LikeLihood Ratio (LLR) value of each bit by using a posteriori probability of each bit for the signal determined based on an equalization matrix and a likelihood value for the signal; and decoding the signal by using the LLR value.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system for supporting higher data rates Beyond 4th-Generation (4G) communication systems such as Long Term Evolution (LTE). A method for operating a receiver in a wireless communication system may include: receiving a signal from a transmitter; performing Integer Forcing (IF) equalization on the received signal; determining a log LikeLihood Ratio (LLR) value of each bit by using a posteriori probability of each bit for the signal determined based on an equalization matrix and a likelihood value for the signal; and decoding the signal by using the LLR value.