Abstract: An encoding/decoding apparatus and method for controlling a channel signal is disclosed, wherein the encoding apparatus may include an encoder to encode an object signal, a channel signal, and rendering information for the channel signal, and a bit stream generator to generate, as a bit stream, the encoded object signal, the encoded channel signal, and the encoded rendering information for the channel signal.

Abstract: The present invention discloses an encoding apparatus using a Discrete Cosine Transform (DCT) scanning, which includes a mode selection means for selecting an optimal mode for intra prediction; an intra prediction means for performing intra prediction onto video inputted based on the mode selected in the mode selection means; a DCT and quantization means for performing DCT and quantization onto residual coefficients of a block outputted from the intra prediction means; and an entropy encoding means for performing entropy encoding onto DCT coefficients acquired from the DCT and quantization by using a scanning mode decided based on pixel similarity of the residual coefficients.

Abstract: A non-volatile memory device includes a substrate; a first conductive layer over the substrate, a second conductive layer over the first conductive layer, a stacked structure disposed over the second conductive layer, wherein the stacked structure includes a plurality of first inter-layer dielectric layers and a plurality of third conductive layers alternately stacked, a pair of first channels that penetrate the stacked structure and the second conductive layer, a second channel which is buried in the first conductive layer, covered by the second conductive layer, and coupled to lower ends of the pair of the first channels; and a memory layer formed along internal walls of the first and second channels.

Abstract: A non-volatile memory device includes a substrate including a cell region and a peripheral circuit region, a first insulation layer formed over the substrate to cover the peripheral circuit region thereof, and interlayer dielectric patterns and first conductive patterns alternately formed over the substrate of the cell region. Each of the interlayer dielectric patterns and the first conductive patterns includes a horizontal part extending along a surface of the substrate and a vertical part extending along a sidewall of the first insulation layer.

Abstract: A semiconductor device includes a word line, a bit line crossing the word line, an active region arranged in an oblique direction at the word line and the bit line, and a contact pad contacting the active region, where the contact pad extends in the oblique direction.

Abstract: A non-volatile memory device includes a substrate including a cell region and a peripheral circuit region, a first insulation layer formed over the substrate to cover the peripheral circuit region thereof, and interlayer dielectric patterns and first conductive patterns alternately formed over the substrate of the cell region. Each of the interlayer dielectric patterns and the first conductive patterns includes a horizontal part extending along a surface of the substrate and a vertical part extending along a sidewall of the first insulation layer.

Abstract: A non-volatile memory device includes a substrate; a first conductive layer over the substrate, a second conductive layer over the first conductive layer, a stacked structure disposed over the second conductive layer, wherein the stacked structure includes a plurality of first inter-layer dielectric layers and a plurality of third conductive layers alternately stacked, a pair of first channels that penetrate the stacked structure and the second conductive layer, a second channel which is buried in the first conductive layer, covered by the second conductive layer, and coupled to lower ends of the pair of the first channels; and a memory layer formed along internal walls of the first and second channels.

Abstract: A semiconductor device includes a bit line formed over a substrate, an insulation layer formed over the bit line, a gate line crossing the bit line and formed over the insulation layer, and a channel layer formed on both sidewalls of the gate line and coupled to the bit line.

Abstract: A semiconductor device that secures a contact margin between a storage node contact plug and an active region and a method for fabricating the same. A method for fabricating a semiconductor device includes forming a device isolation layer defining active regions extending in a first direction a substrate, forming a first trench extending across the active regions and the device isolation layer by selectively etching the substrate, forming a second trench under the first trench to isolate the active regions which are adjacent in the first direction by selectively etching the substrate, and forming a gate electrode filling the first and second trenches.

Abstract: A semiconductor device and method for fabricating the same is provided. The semiconductor device includes a trench formed in a substrate, a junction region formed in the substrate on both sides of the trench, a first gate insulation layer formed on the surface of the trench, a first buried conductive layer formed over the first gate insulation layer to fill a portion of the trench, a second buried conductive layer formed between the first buried conductive layer and the first gate insulation layer to provide a gap between the first buried conductive layer and the first gate insulation layer, and a second gate insulation layer buried in the gap.

Abstract: A semiconductor device includes a word line, a bit line crossing the word line, an active region arranged in an oblique direction at the word line and the bit line, and a contact pad contacting the active region, where the contact pad extends in the oblique direction.

Abstract: A semiconductor device and method for fabricating the same is provided. The semiconductor device includes a trench formed in a substrate, a junction region formed in the substrate on both sides of the trench, a first gate insulation layer formed on the surface of the trench, a first buried conductive layer formed over the first gate insulation layer to fill a portion of the trench, a second buried conductive layer formed between the first buried conductive layer and the first gate insulation layer to provide a gap between the first buried conductive layer and the first gate insulation layer, and a second gate insulation layer buried in the gap.

Abstract: A method for forming a fin transistor includes forming a fin active region, depositing a thin layer doped with impurities over a semiconductor substrate, and forming a channel by diffusing the impurities into the fin active region of the fin transistor. In detail of the fin transistor formation, a fin active region is formed, and a patterned pad nitride layer is formed over the fin active region. A thin layer containing boron is deposited over the fin active region and isolation regions. Boron in the thin layer is diffused into the fin active region to form a channel.

Abstract: First gate lines are formed on a substrate. An insulation layer is formed on the substrate and the first gate lines. The insulation layer disposed between the first gate lines is selectively etched, to thereby form first openings. Landing plugs are buried into the first openings. The insulation layer disposed on the first gate lines is etched until upper portions of the first gate lines are exposed, thereby obtaining second openings. Second gate lines are formed inside the second openings.

Abstract: Disclosed are a semiconductor device with a device isolation structure and a method for fabricating the same. The method includes the steps of: forming a plurality of trenches defining first active regions by etching a substrate in a predetermined depth; forming a plurality of first device isolation layers in inner sides of the plurality of trenches; forming a plurality of second device isolation layers on the plurality of first device isolation layers as remaining a space opening an upper portion of each first active region disposed between the second device isolation layers; and forming a plurality of second active regions connected to the first active region between the second device isolation layers.

Abstract: A method for fabricating a semiconductor device includes forming a fuse line over a first region of a substrate, forming a first insulation layer over the fuse line and the substrate, forming a capacitor including an electrode over a second region of the substrate, such that a conductive layer for the electrode is patterned over the first insulation layer of the first region to overlap with the fuse line, forming a second insulation layer over the capacitor, etching the second insulation layer using the patterned conductive layer of the first region as an etch stop layer, and etching the patterned conductive layer and the first insulation layer to make a portion of the first insulation layer remain over the fuse line at a certain thickness.

Abstract: An improved method of fabricating a contact plug is described herein. The method includes forming a first insulation layer including a first contact hole over a substrate, forming protection layers on both sidewalls of the first contact hole, filling the first contact hole with a conductive material to form a first contact plug, forming a second insulation layer over the first insulation layer and the first contact plug, and forming a second contact hole exposing the first contact plug by etching a portion of the second insulation layer.

Abstract: A method for forming a fin transistor includes forming a fin active region, depositing a thin layer doped with impurities over a semiconductor substrate, and forming a channel by diffusing the impurities into the fin active region of the fin transistor. In detail of the fin transistor formation, a fin active region is formed, and a patterned pad nitride layer is formed over the fin active region. A thin layer containing boron is deposited over the fin active region and isolation regions. Boron in the thin layer is diffused into the fin active region to form a channel.

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a plurality of gate lines over a substrate, wherein the substrate is defined into a cell region and a peripheral region, forming a gate spacer layer over the gate lines, the gate spacer layer including a buffer layer, an insulation layer, and a barrier layer, forming a mask pattern over the barrier layer in a manner to cover the cell region and open the peripheral region, performing an anisotropic etching method on the gate spacer layer using the mask pattern as an etch mask to form gate spacers on sidewalls of the gate lines in the peripheral region, performing an ion implantation process to form source/drain regions in the peripheral region, and simultaneously removing the mask pattern and the barrier layer.

Abstract: First gate lines are formed on a substrate. An insulation layer is formed on the substrate and the first gate lines. The insulation layer disposed between the first gate lines is selectively etched, to thereby form first openings. Landing plugs are buried into the first openings. The insulation layer disposed on the first gate lines is etched until upper portions of the first gate lines are exposed, thereby obtaining second openings. Second gate lines are formed inside the second openings.