Abstract: A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.

Abstract: Embodiments relate to half-duplex bidirectional transmission of data compliant with a first standard (e.g., Universal Serial Bus (USB) standard) over a physical channel of a multimedia link for transmitting audio/video (“A/V”) data compliant with a second standard (e.g., Mobile High-Definition Link (MHL) standard) between a source device and a sink device using time division multiplexing (TDM). The source device sends units of data including A/V data and forward data compliant with the first standard at first times whereas the sink device sends units of data including backward data compliant with the first standard at second times between transmissions from the source device. The first times do not overlap with the second times. Synchronization signals may be added to the first and second units of data to align character symbols embedded in the first and second units of data.

Abstract: Techniques and mechanisms for exchanging communications which each represent a respective combination of data and clock signaling. In an embodiment, encoder logic generates a first signal pair, including encoding a first differential data signal pair with a first clock signal of a differential clock signal pair. The encoder logic further generates a second signal pair, including encoding a second differential data signal pair with a second clock signal of the same differential clock signal pair. In another embodiment, decoder logic receives and decodes the first signal pair and the second signal pair, wherein the decoding generates the first differential data signal pair, the second differential data signal pair and a clock signal.

Abstract: Embodiments relate to half-duplex bidirectional transmission of data compliant with a first standard (e.g., Universal Serial Bus (USB) standard) over a physical channel of a multimedia link for transmitting audio/video (“A/V”) data compliant with a second standard (e.g., Mobile High-Definition Link (MHL) standard) between a source device and a sink device using time division multiplexing (TDM). The source device sends units of data including A/V data and forward data compliant with the first standard at first times whereas the sink device sends units of data including backward data compliant with the first standard at second times between transmissions from the source device. The first times do not overlap with the second times. Synchronization signals may be added to the first and second units of data to align character symbols embedded in the first and second units of data.

Abstract: A method, apparatus and system for pre-authenticating ports is disclosed. In one embodiment, an active port facilitating communication of media content between a transmitting device and a receiving device is identified, while the active port are associated with a first High-Definition Content Protection (HDCP) engine. Then, inactive ports that are in idle mode serving as backup ports to the active port are identified, while the inactive ports are associated with a second HDCP engine. Pre-authentication of each of the inactive ports is performed so the pre-authenticated inactive ports can subsequently replace the active port if a port switch is performed.

Abstract: Embodiments of the invention are generally directed to a low power standby mode control circuit. An embodiment of an apparatus includes a processor, an interface for a connection with a second apparatus, and an operational circuit, wherein the processor is to disable one or more power connections to the operational circuit in a standby mode. The apparatus further includes a standby mode control circuit, the standby control circuit to operate using a standby power source, wherein the standby mode control circuit is to detect a stimulus signal from the second apparatus and in response to the stimulus signal the standby control circuit is to signal the processor, the processor to enable the one or more power connections of the operational circuit.

Abstract: A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.

Abstract: A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.

Abstract: Techniques and mechanisms for exchanging communications which each represent a respective combination of data and clock signaling. In an embodiment, encoder logic generates a first signal pair, including encoding a first differential data signal pair with a first clock signal of a differential clock signal pair. The encoder logic further generates a second signal pair, including encoding a second differential data signal pair with a second clock signal of the same differential clock signal pair. In another embodiment, decoder logic receives and decodes the first signal pair and the second signal pair, wherein the decoding generates the first differential data signal pair, the second differential data signal pair and a clock signal.

Abstract: A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.

Abstract: A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.

Abstract: Discovery of connections utilizing a control bus. An embodiment of a method includes detecting a transition of a control bus from a high state to a low state by a source device, the source device being configured to be coupled with a sink device via an interface, the interface including the control bus, the source device including a pullup device and the sink device including a pulldown device; pulsing the control bus to a high state at the source device; and upon detecting by the source device that the control bus remains in the high state ceasing the pulsing of the control bus to the high state, and transitioning the source device from a disconnected state to a connected state.

Abstract: Embodiments of the invention are generally directed to a low power standby mode control circuit. An embodiment of an apparatus includes a processor, an interface for a connection with a second apparatus, and an operational circuit, wherein the processor is to disable one or more power connections to the operational circuit in a standby mode. The apparatus further includes a standby mode control circuit, the standby control circuit to operate using a standby power source, wherein the standby mode control circuit is to detect a stimulus signal from the second apparatus and in response to the stimulus signal the standby control circuit is to signal the processor, the processor to enable the one or more power connections of the operational circuit.

Abstract: Transmission of alternative content over standard device connectors. An embodiment of a method includes connecting a first device to a second device utilizing a standard connector, the connector including multiple pins, and detecting whether the second device is operating in a standard mode or an alternative mode. If the second device is operating in the alternative mode, then switching one or more pins of the standard connector for the alternative mode and transmitting or receiving signals for the alternative mode via the plurality of pins of the standard connector.

Abstract: A method, apparatus and system for employing an automatic data aligner for multiple serial receivers in serial link technologies is provided. In one embodiment, converting a transmission data path of a single bit into a parallel bit via a data aligner, wherein the data is being transmitted via one or more ports. Further, binding data transmission channels to reduce latency in transmission of the data, wherein the binding of the data transmission channels further includes inserting delay to match latency via the one or more ports.

Abstract: A method, apparatus and system employing a 17B/20B coder is disclosed. The 17B/20B coder to receive an incoming stream including a 17B block and a 20B block, and partition the 17B block into first blocks, and partitioning the 20B into second blocks. The coder is further to code 17B to 20B of memory using one or more serial lines for communication is performed, wherein coding includes coding the first blocks of the 17B block and the second blocks of the 20B block, wherein the coding of the first and second blocks is performed such that a maximum run length is maintained.

Abstract: A method and system for inter-port communication utilizing a multi-port memory device. The memory device contains an interrupt register, an interrupt signal interface (e.g., a dedicated pin), an interrupt mask, and one or more message buffers associated with each port. When a first component coupled to a first port of the memory device wants to communicate with a second component coupled to a second port of the memory device, the first component writes a message to a message buffer associated with the second port. An interrupt in the input register of the second port is set to notify the second component coupled to the second port that a new message is available. Upon receiving the interrupt, the second component reads the interrupt register to determine the nature of the interrupt. The second component then reads the message from the message buffer.

Abstract: Discovery of electronic devices utilizing a control bus. An embodiment of a method includes connecting a receiving device to a cable, where the cable includes a control bus. If the receiving device is in a disconnect state and a signal from a transmitting device is detected on the control bus, the device is transferred to a state for a first type of transmitting device. If the receiving device is in either the disconnect state or the state for the first type of transmitting device and a predetermined voltage signal is received from the transmitting device, then the receiving device is transferred to a state for a second type of transmitting device.

Abstract: In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first chip to transmit first and second differential signals on conductors, and a second chip. The second chip includes receivers to receive the first and second differential signals from the conductors and provide received signals representative thereof, and current mode circuitry to selectively modulate a common mode voltage of either the first or second differential signals to communicate data and wherein the first chip includes common mode detection circuitry to detect changes in the common mode voltage. Other embodiments are described and claimed.

Abstract: A method, apparatus and system employing a 17 B/20 B coder is disclosed. The 17 B/20 B coder to receive an incoming stream including a 17 B block and a 20 B block, and partition the 17 B block into first blocks, and partitioning the 20 B into second blocks. The coder is further to code 17 B to 20 B of memory using one or more serial lines for communication is performed, wherein coding includes coding the first blocks of the 17 B block and the second blocks of the 20 B block, wherein the coding of the first and second blocks is performed such that a maximum run length is maintained.