Abstract: A vertical III-V Hall sensor, which has a substrate layer with an upper side and an underside, and a first insulating layer formed on the substrate layer, and a III-V semiconductor layer formed on the insulating layer, and a second insulating layer formed on the III-V semiconductor layer, the second insulating layer being structured and having at least three openings designed as contact regions, and the III-V semiconductor layer having a length formed in the X direction and a width formed in the Y direction, and the at least three contact regions being arranged along a straight line, and the III-V semiconductor layer having an n doping, and the III-V semiconductor layer having a peripheral insulation.

Abstract: A method produces a transistor, in particular a gallium nitride transistor based on high electron mobility. After a structured metal layer has been formed in a first gate region by a temporarily formed structured first photoresist layer, an intermediate layer has been deposited and a second insulation layer has been deposited, a second photoresist layer is structured in order to expose a second gate region, wherein subsequently a first field plate and a second field plate are formed as buried field plates on respective sides of the second gate region.

Abstract: A method produces a transistor, in particular a gallium nitride transistor based on high electron mobility. After a structured metal layer has been formed in a first gate region by a temporarily formed structured first photoresist layer, an intermediate layer has been deposited and a second insulation layer has been deposited, a second photoresist layer is structured in order to expose a second gate region, wherein subsequently a first field plate and a second field plate are formed as buried field plates on respective sides of the second gate region.

Abstract: The invention relates to an electronic component having a circuit integrated on a semiconductor substrate, and a heat-conducting connection of the substrate by soldering using a carrier serving as a heat sink, wherein the invention proposes depositing a first, thicker Au layer (23) in the conventional back-side metallization of the substrate, thereafter a barrier coating (24), and, as the last layer, a thinner, second Au layer (25), wherein the material of the barrier coating is selected such that the barrier coating prevents the penetration by means of a diffusion barrier of Sn or AuSn from a liquid Au—Sn phase in the region of the second Au layer into the first Au layer (23) during the soldering process. The layer sequence of the back-side metallization is also deposited in the pass-through openings of the substrate, wherein the surface of the second Au layer comprises a reduced coatablity for the solder material due to the material diffused out of the barrier coating.

Abstract: The invention relates to an electronic component having a circuit integrated on a semiconductor substrate, and a heat-conducting connection of the substrate by soldering using a carrier serving as a heat sink, wherein the invention proposes depositing a first, thicker Au layer (23) in the conventional back-side metallization of the substrate, thereafter a barrier coating (24), and, as the last layer, a thinner, second Au layer (25), wherein the material of the barrier coating is selected such that the barrier coating prevents the penetration by means of a diffusion barrier of Sn or AuSn from a liquid Au—Sn phase in the region of the second Au layer into the first Au layer (23) during the soldering process. The layer sequence of the back-side metallization is also deposited in the pass-through openings of the substrate, wherein the surface of the second Au layer comprises a reduced coatablity for the solder material due to the material diffused out of the barrier coating.

Abstract: The production of a microelectronic component, particularly a pHEMT, having a T-shaped gate electrode in a double-recess structure uses a production method for self-adjusting alignment of the two recesses of the double-recess structure and of the gate foot of the gate electrode.

Abstract: A method for producing a semiconductor component, and a semiconductor component, having a metallic gate electrode deposited onto a semiconductor layer, with the gate electrode having a gate foot and a gate head. The component is produced by depositing a first layer of aluminum on the semiconductor layer, depositing a second layer of a second metal on the first layer, depositing at least one additional layer (G3) of an additional metal, different from the second metal, on the second layer, and carrying out a temperature treatment at elevated temperature.

Abstract: A semiconductor component, particularly a pHEMT, having a T-shaped gate electrode deposited in a double-recess structure, is produced with a method with self-adjusting alignment of the recesses and of the T-shaped gate electrode.

Abstract: A method for producing a gate head which can be precisely scaled and for reducing parasitic capacities, for a semiconductor component comprising an at least approximately T-shaped electrode.

Abstract: A semiconductor component, particularly a pHEMT, having a T-shaped gate electrode deposited in a double-recess structure, is produced with a method with self-adjusting alignment of the recesses and of the T-shaped gate electrode.

Abstract: The production of a microelectronic component, particularly a pHEMT, having a T-shaped gate electrode in a double-recess structure uses a production method for self-adjusting alignment of the two recesses of the double-recess structure and of the gate foot of the gate electrode.

Abstract: A method for producing a semiconductor component, and a semiconductor component, having a metallic gate electrode deposited onto a semiconductor layer, with the gate electrode having a gate foot and a gate head. The component is produced by depositing a first layer of aluminum on the semiconductor layer, depositing a second layer of a second metal on the first layer, depositing at least one additional layer (G3) of an additional metal, different from the second metal, on the second layer, and carrying out a temperature treatment at elevated temperature.

Abstract: A method for the production of individual integrated circuit arrangements from a wafer composite is disclosed, whereby the wafer is fixed with the component side (FS) on a support, the individual circuit arrangements (21) are separated on the support body by the etching of separating trenches (27) and individually lifted from the support body. The semiconductor substrate (20) is reduced in thickness during the fixing of the wafer to the support body, preferably to a substrate thickness of less than 100 ?m. A reverse face metallization (31) is deposited on the back face (RS) of the thinned substrate, preferably after separation of the circuit arrangements on the support body.

Abstract: Methods are specified for producing passive components on a substrate, which methods permit, with a low outlay and a good yield, the production of different components, in particular high-resistance and low-resistance resistor elements and/or capacitor elements having a higher and those having a lower capacitance per unit length on a substrate. In this case, lift-off processes can largely be dispensed with, particularly in the case of critical patternings, and selective dry- and/or wet-chemical etching can be effected.

Abstract: A method for producing a gate head which can be precisely scaled and for reducing parasitic capacities, for a semiconductor component comprising an at least approximately T-shaped electrode.

Abstract: A method for producing a gate head which can be precisely scaled and for reducing parasitic capacities, for a semiconductor component comprising an at least approximately T-shaped electrode.

Abstract: A method for the production of individual integrated circuit arrangements from a wafer composite is disclosed, whereby the wafer is fixed with the component side (FS) on a support, the individual circuit arrangements (21) are separated on the support body by the etching of separating trenches (27) and individually lifted from the support body. The semiconductor substrate (20) is reduced in thickness during the fixing of the wafer to the support body, preferably to a substrate thickness of less than 100 ?m. A reverse face metallization (31) is deposited on the back face (RS) of the thinned substrate, preferably after separation of the circuit arrangements on the support body.

Abstract: A hetero-bipolar transistor on Ga—As basis which has an advantageous design and to a method for producing the same which allows production of inexpensive and long-term stable components.

Abstract: The invention relates to a semiconductor component with a WSiN layer as thin-film resistor with high temperature coefficient for use as thermistor in bolometers. The production method comprises thermal decoupling by means of thermistors that are free-standing or disposed on an insulation layer.

Abstract: Methods are specified for producing passive components on a substrate, which methods permit, with a low outlay and a good yield, the production of different components, in particular high-resistance and low-resistance resistor elements and/or capacitor elements having a higher and those having a lower capacitance per unit length on a substrate. In this case, lift-off processes can largely be dispensed with, particularly in the case of critical patternings, and selective dry-and/or wet-chemical etching can be effected.