Abstract: A circuit for protecting a MOSFET power transistor, the circuit having a variable input impedance in which the rate of rise of voltage is to be increased and thus the switching time reduced. For this purpose, a second MOSFET auxiliary transistor is connected by its bulk electrode to the source of the MOSFET power transistor. The source of the second MOSFET auxiliary transistor is connected to the gate of a third MOSFET auxiliary transistor and to the gate of the MOSFET power transistor. The drain of the second MOSFET auxiliary transistor is connected to a circuit input terminal which is coupled by a resistor to the gate of the MOSFET power transistor. The gate of the second MOSFET auxiliary transistor is connected to the drain of the second MOSFET auxiliary transistor as well as to the source of the third MOSFET auxiliary transistor.