Abstract: An apparatus and method is disclosed for reducing error propagation in a decision feedback equalizer by constraining the values of feedback filter tap coefficients in a feedback filter of the decision feedback equalizer. The feedback filter tap coefficients that are constrained are calculated using a constraint cost function and a related constraint function. The constraint condition of the present invention reduces error propagation in a decision feedback equalizer by preventing error from circulating in a feedback loop of a feedback filter within the decision feedback equalizer.

Abstract: An apparatus and method is disclosed for estimating timing error in a digital signal receiver from a difference between an arrival time of a first training sequence and an arrival time of a second training sequence in the digital signal receiver. Time domain representations of the timing sequence data are converted into frequency domain representations and used to calculate a complex cross power spectrum. The timing error is obtained by determining an average phase of the complex cross power spectrum. The timing error is then used to calculate an accurate value for the clock rate of the digital signal transmitter.

Abstract: Robust and existing standard bit streams are mixed in a backward compatible manner for forming enhanced modes for better reception of ATSC DTV signals. This is achieved by an enhanced coding block provided at the input of a conventional ATSC trellis encoder unit. The enhanced coding block comprising a trellis encoder encodes only the robust stream while passing the normal standard stream unaltered.

Abstract: A channel decoder employs a hybrid frequency-time domain equalizer for effectively combining a frequency domain equalizer with a time domain equalizer to achieve superior static and dynamic multi-path performance compared to conventional decision feedback equalizers. A frequency domain equalizer structure is included within the forward path of a time domain, decision feedback equalizer, with both the frequency domain and time domain portions employing a common error vector. Updates to the taps (frequency bins) may be adapted individually, or fully within the frequency domain without altering the feedback filter. Improved performance, including performance for noisy channels with deep notches, is achieved, and the frequency domain equalizer portion is relieved from equalizing minimum phase zeros of the channel.

Abstract: A digital transmission system and method that improves upon the ATSC A/53 HDTV signal transmission standard includes: a first forward error correction (FEC) unit for encoding packets belonging to each of robust and normal data bit streams; a robust processor unit for receiving robust packets comprising priority data and processing the packets for generating the robust bit stream; a trellis encoder unit for producing a stream of trellis encoded data bits corresponding to bits of the normal and robust streams, the encoder employing mapping of encoded data bits of said robust packets into symbols according to one or more symbol mapping schemes; and, an optional second forward error correction (FEC) encoding unit for ensuring backward compatibility with a receiver device by reading in only packets of the robust bit stream and enabling generation of parity bytes only for the robust stream packets; and, a transmitter device for transmitting the robust bit streams in a backwards compatible manner, separately or in c

Abstract: A flexible digital transmission system that improves upon the ATSC A/53 HDTV signal transmission standard. The system includes a digital signal transmitter for generating a first Advanced Television Systems Committee (ATSC) standard encoded 8-VSB bit stream and, for generating an encoded new robust bit stream for transmitting high priority information bits, wherein symbols of the new bit stream are capable of being transmitted according to a transmission mode including: a 2-VSB mode and a 4-VSB transmission mode. The standard 8-VSB bit stream and new bit stream may be simultaneously transmitted over a terrestrial channel according to a broadcaster defined bit-rate ratio. The transmission system includes a control mechanism for generating information needed for encoding robust packets at a transmitter device. It also includes a mechanism for encoding control parameters and multiplexes the generated information with the standard and robust bit-streams for transmission.

Abstract: This disclosure describes a flexible digital transmission system that improves upon the ATSC A/53 HDTV signal transmission standard. The system includes a digital television signal transmitter for generating a first Advanced Television Systems Committee (ATSC) standard 8-VSB bit stream and, for generating an encoded new bit stream capable of transmitting high priority information bits, wherein symbols of the new bit stream are capable of being transmitted according to a transmission mode selected from group comprising: a 2-VSB mode, a 4-VSB mode, and a hierarchical-VSB (H-VSB) transmission mode. Each respective 2-VSB, 4-VSB, and H-VSB mode is characterized as having symbols mapped according to possible symbol values from an alphabet comprising respectively, {−7, −5, 5, 7}, {7, 3, −3, −7}, and {7, 5, 3, −3, −5, −7}.

Abstract: A decision feedback equalizer (DFE) includes a forward equalizer, first and second adders, a decision device, a feedback equalizer, and an N-tap filter. Preferably, the first and second adders, the decision device, and the feedback equalizer constitute a first feedback loop, the second adder, the decision device, and the N-tap filter constitute a second feedback loop. In that case, the second feedback loop is free of an implementation delay associated with the first feedback loop. In the exemplary DFE, N is a positive integer. If desired, the N-tap filter is implemented in fast logic. A method for controlling a decision feedback equalizer based on first and second feedback signals is also described.

Abstract: A round off mechanism maintains a mean value of the operand while rounding twos complement binary data. Positive data values are incremented at the first discard bit prior to truncation of the discard bits, as are negative data values having a one within the most significant discard bit and at least one other discard bit. The discard bits are simply truncated for all other negative data values.

Abstract: For use in a receiver capable of decoding trellis encoded signals, there is disclosed an apparatus and method for reducing error propagation in a two stage decision feedback equalizer. The apparatus of the invention comprises a first stage equalizer comprising a first forward equalizer filter, a first decision feedback equalization filter, and a trellis decoder. The apparatus of the invention also comprises a second stage equalizer comprising a second forward equalizer filter and a second feedback equalization filter. The two stage decision feedback equalizer is capable of obtaining symbol values from the trellis decoder and using the symbol values as estimates in channel equalization. In one embodiment of the invention, a two stage decision feedback equalizer is provided in which forward filter coefficients remain constant for the duration of D symbols.

Abstract: This invention provides a method for initializing the filter coefficients of a hybrid frequency-time domain adaptive equalizer device implementing frequency domain (FD) filter equalization in a forward path and a time domain (TD) filter equalization in a feedback path, with each filter unit having a plurality of adaptable filter taps.

Abstract: A multiplier device for multiplying one of a discrete set of digital level values with a filter coefficient in a filter device implemented in a decision feedback equalizer comprises: a decoder device for receiving a discrete digital level value to be multiplied and generating control signals according to the digital level value; an inverter circuit providing two parallel operations, each operation including multiplying the determined number by either +1/−1 in accordance with the control signals for generating two intermediate results; a multiplier circuit receiving the two intermediate results and providing respective parallel operations for multiplying a corresponding intermediate result by +1 or zero (0) in accordance with a control signal and generating further intermediate results; a logic circuit for shifting bits of one further intermediate result to effect a multiplication of one of the further intermediate output result with a discrete digital level value different than any of the orig

Abstract: For use in a receiver capable of decoding trellis encoded signals of the type comprising a trellis decoder and a decision feedback equalizer coupled to each path memory output of said trellis decoder, wherein said decision feedback equalizer is capable of obtaining symbol values from each path memory output of said trellis decoder for use as estimates in channel equalization, an apparatus and method is disclosed for reconstructing symbol values from trace back path information stored within said trellis decoder. The apparatus and method of the present invention reconstructs a symbol stream from the trellis decoder using data signal selection circuitry to obtain bit values that represent the reconstructed symbols. In one embodiment of the present invention, each of a plurality of multiplexers selects one of four symbol value inputs to send to a first adaptive filter tap cell in a set of twelve adaptive filter tap cells.

Abstract: A single integrated circuit multi-standard demodulator includes an adaptive inverse channel estimator for frequency domain equalization which employs a recursive least square cost function in estimating the inverse channel from the received signal and an error estimate. Utilizing a diagonal correlation matrix, the solution to may be determined utilizing fewer computational resources than required by conventional frequency domain equalizers, shifting from a computational intensive to memory intensive implementation. The memory requirement is fully satisfied by memory available within conventional OFDM decoders, and the necessary computational resources may be readily mapped to the resources available within such decoders, improving integrated circuit cost-effectiveness of the multi-standard demodulator.

Abstract: A delay locked loop comprising a chain (CHN) of at least two delay elements (DL1-DLN), of which a first delay element (DL1) has an input for receiving a reference signal (phi0), and of which a last delay element (DLN) has an output for delivering an output signal (phiN); a phase comparator (PHCMP) having a first input (PH1) for receiving the reference signal (phi0), a second input (PH2) for receiving the output signal (phiN), and an output for delivering a binary control signal (Bcntrl); and a converter (CNV) for converting the binary control signal (Bcntrl) into an analog control signal (Acntrl) for controlling a delay time of at least one (DL1-DLN) of said delay elements (DL1-DLN). The phase comparator (PHCMP) comprises at least one additional input (Aip) for receiving an output signal (phi1-phiN−1) of at least one of the delay elements (DL1-DLN−1) preceding the last delay element (DLN).