Patents by Inventor Dah Lin

Dah Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240085739
    Abstract: A wavelength conversion element including a substrate, a blocking wall structure layer, and a wavelength conversion layer is provided. The blocking wall structure layer is disposed on a surface of the substrate and defines multiple microgrooves. Reflectivity of the blocking wall structure layer is in a range of 1% to 99%. The wavelength conversion layer is disposed in the microgrooves and includes multiple wavelength conversion particles. A height of the blocking wall structure layer along a normal direction of the surface of the substrate is greater than a height of the wavelength conversion layer along the normal direction of the surface of the substrate. A backlight module adopting the wavelength conversion element is also provided.
    Type: Application
    Filed: September 4, 2023
    Publication date: March 14, 2024
    Applicant: Nano Precision Taiwan Limited
    Inventors: Ching-Nan Chuang, Hung-Tse Lin, Ming-Dah Liu, Yen-Ni Lin
  • Patent number: 6528366
    Abstract: Methods for fabricating a vertical metal-insulator-metal (MIM) capacitor are described. The capacitor can be fabricated at any level of metal interconnect, depending upon the desired depth of the capacitor. No global topology variations occur at any interconnect level in these methods. The entire process temperature is limited to be low enough, less than about 450° C., so that the back-end metal interconnect is not degraded or damaged. In one method, the deep capacitor cavity can be formed by etching back-end oxide (i.e. intermetal dielectric) from near the top level of metal interconnect until reaching the via-plug at several lower metal interconnect levels. In another method, metal lines and tungsten plugs are formed in both the logic and memory areas. Then, a selective wet metal etching is performed to remove the stacked tungsten plugs and metal lines for the formation of the capacitor cavity.
    Type: Grant
    Filed: April 23, 2001
    Date of Patent: March 4, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yeur-Luen Tu, Dah Lin, Min-Hwa Chi