Abstract: An image sensor includes a pixel array, an analog-to-digital converter (ADC), and a test circuit. The pixel array includes a plurality of pixels arranged in rows and columns. Each pixel generates an analog signal based on incident light. The ADC converts the analog signal to a digital signal using a counter. The test circuit receives a test code in a test mode, generates a count clock signal based on the test code, tests a counting operation of the counter according to the count clock signal, and externally outputs a test result of the counter through a test terminal.

Abstract: An image sensor includes a pixel array, an analog-to-digital converter (ADC), and a test circuit. The pixel array includes a plurality of pixels arranged in rows and columns. Each pixel generates an analog signal based on incident light. The ADC converts the analog signal to a digital signal using a counter. The test circuit receives a test code in a test mode, generates a count clock signal based on the test code, tests a counting operation of the counter according to the count clock signal, and externally outputs a test result of the counter through a test terminal.

Abstract: An image sensor includes a pixel array, an analog-to-digital converter (ADC), and a test circuit. The pixel array includes a plurality of pixels arranged in rows and columns. Each pixel generates an analog signal based on incident light. The ADC converts the analog signal to a digital signal using a counter. The test circuit receives a test code in a test mode, generates a count clock signal based on the test code, tests a counting operation of the counter according to the count clock signal, and externally outputs a test result of the counter through a test terminal.

Abstract: An image sensor includes a pixel array, an analog-to-digital converter (ADC), and a test circuit. The pixel array includes a plurality of pixels arranged in rows and columns. Each pixel generates an analog signal based on incident light. The ADC converts the analog signal to a digital signal using a counter. The test circuit receives a test code in a test mode, generates a count clock signal based on the test code, tests a counting operation of the counter according to the count clock signal, and externally outputs a test result of the counter through a test terminal.

Abstract: The image sensor includes a first analog-to-digital converter configured to convert a first analog pixel signal output from a first pixel in a row into first digital signals, a second analog-to-digital converter configured to convert a second analog pixel signal output from a second pixel in the row into second digital signals, a first output circuit configured to output a first bit value at a first position in the first digital signals in response to a first enable control signal, and a second output circuit configured to output a second bit value at a second position in the second digital signals in response to a second enable control signal, the second position in the second digital signals corresponding to the first position in the first digital signals, wherein the second enable control signal is activated with a delay from the activation of the first enable control signal.

Abstract: The image sensor includes a first analog-to-digital converter configured to convert a first analog pixel signal output from a first pixel in a row into first digital signals, a second analog-to-digital converter configured to convert a second analog pixel signal output from a second pixel in the row into second digital signals, a first output circuit configured to output a first bit value at a first position in the first digital signals in response to a first enable control signal, and a second output circuit configured to output a second bit value at a second position in the second digital signals in response to a second enable control signal, the second position in the second digital signals corresponding to the first position in the first digital signals, wherein the second enable control signal is activated with a delay from the activation of the first enable control signal.