Patents by Inventor Dah Wen Tsang

Dah Wen Tsang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8110888
    Abstract: High voltage semiconductor devices with high-voltage termination structures are constructed on lightly doped substrates. Lightly doped p-type substrates are particularly prone to depletion and inversion from positive charges, degrading the ability of associated termination structures to block high voltages. To improve the efficiency and stability of termination structures, second termination regions of the same dopant type as the substrate, more heavily doped than the substrate but more lightly doped than first termination regions, are positioned adjoining the first termination regions. The second termination regions raise the field threshold voltage where the surface is vulnerable and render the termination structure substantially insensitive to positive charges at the surface. The use of higher dopant concentration in the gap region without causing premature avalanche is facilitated by only creating second termination regions for regions lacking field plate protection.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: February 7, 2012
    Assignee: Microsemi Corporation
    Inventors: Jinshu Zhang, Dumitru Sdrulla, Dah Wen Tsang
  • Publication number: 20090072340
    Abstract: High voltage semiconductor devices with high-voltage termination structures are constructed on lightly doped substrates. Lightly doped p-type substrates are particularly prone to depletion and inversion from positive charges, degrading the ability of associated termination structures to block high voltages. To improve the efficiency and stability of termination structures, second termination regions of the same dopant type as the substrate, more heavily doped than the substrate but more lightly doped than first termination regions, are positioned adjoining the first termination regions. The second termination regions raise the field threshold voltage where the surface is vulnerable and render the termination structure substantially insensitive to positive charges at the surface. The use of higher dopant concentration in the gap region without causing premature avalanche is facilitated by only creating second termination regions for regions lacking field plate protection.
    Type: Application
    Filed: September 9, 2008
    Publication date: March 19, 2009
    Applicant: MICROSEMI CORPORATION
    Inventors: Jinshu Zhang, Dumitru Sdrulla, Dah Wen Tsang
  • Publication number: 20020074585
    Abstract: A power MOSFET transistor is formed on a substrate including a source, body layer, and drain layer and an optional fourth layer for an IGBT. The device is characterized by a conductive gate having a high conductivity metal layer coextensive with a polysilicon layer for high power and high speed operation.
    Type: Application
    Filed: February 22, 2002
    Publication date: June 20, 2002
    Applicant: ADVANCED POWER TECHNOLOGY, INC., Delaware corporation
    Inventors: Dah Wen Tsang, John W. Mosier, Douglas A. Pike, Theodore O. Meyer
  • Patent number: 5801417
    Abstract: A recessed gate power MOSFET is formed on a substrate (20) including a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. A trenching protective layer (30) formed on the substrate upper surface (28) is patterned to define exposed areas (46) as stripes or a matrix, and protected areas. Sidewall spacers (44) of predetermined thickness (52) with inner surfaces (48) contact the protective layer sidewalls. A first trench (50) is formed in substrate areas (46) with sidewalls aligned to the sidewall spacer outer surfaces (47) and extending depthwise through the P-body layer (26) to at least a predetermined depth (56). Gate oxide (60) is formed on the trench walls and gate polysilicon (62) refills the trench to a level (64) near substrate upper surface (28). Oxide (68) between sidewall spacers (44) covers polysilicon (62). Removing the protective layer exposes upper substrate surface (28') between spacer inner surfaces (48).
    Type: Grant
    Filed: August 13, 1993
    Date of Patent: September 1, 1998
    Assignee: Advanced Power Technology, Inc.
    Inventors: Dah Wen Tsang, John W. Mosier, II, Douglas A. Pike, Jr., Theodore O. Meyer
  • Patent number: 5648283
    Abstract: A gate power MOSFET on substrate (20) has a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. Layer (430) on surface (28) patterns areas (446) as stripes or a matrix, and protected areas. Undercut sidewalls (444) of thickness (452), with protruding rims (447), contact the sides of layer (434'). Trench (450) in areas (446) has silicon sidewalls aligned to oxide sidewall (447) and extending depthwise through P-body layer (26) to depth (456). Gate oxide (460) is formed on the trench walls and gate polysilicon (462) refills trench (450) to a level (464) near surface (28) demarcated by the undercut sidewall rims (447). Oxide (468) between spacers (444) covers polysilicon (462). Removing layer (430) exposes surface (28') between the sidewalls (444). Source layer (72) is doped atop the body layer (26') and then trenched to form trench (80) having sidewalls aligned to inner side faces of sidewalls (444).
    Type: Grant
    Filed: January 31, 1994
    Date of Patent: July 15, 1997
    Assignee: Advanced Power Technology, Inc.
    Inventors: Dah Wen Tsang, Dumitru Sdrulla, Douglas A. Pike, Jr., Theodore O. Meyer, John W. Mosier, II, deceased