Patents by Inventor Dahcheng Lin

Dahcheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5930625
    Abstract: A method for creating a stacked, or crown shaped, capacitor structure, with increased surface area, obtained using a storage node electrode, comprised of HSG silicon grains on the surface of the storage node electrode, has been developed. An in situ procedure, allows HSG silicon seeds to be selectively formed, only on the exposed surfaces of a amorphous silicon storage node electrode shape, in an LPCVD system, directly after an HF preclean step. A subsequent anneal, again performed in situ, in the LPCVD system, results in the formation of HSG silicon grains, converted from the HSG silicon seeds.
    Type: Grant
    Filed: April 24, 1998
    Date of Patent: July 27, 1999
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Dahcheng Lin, Jung-Ho Chang, Hsi-Chuan Chen
  • Patent number: 5913119
    Abstract: A process creating a crown shaped storage node electrode, for high density, DRAM designs, has been developed. The process features the formation of an hemispherical grain, (HSG), silicon layer, only on the outside walls of the amorphous silicon vertical shapes, of the crown shaped storage node electrode. The HSG silicon layer is formed from HSG silicon seeds, and from undoped, or lightly doped amorphous silicon layers, or a combination of both. The amorphous silicon vertical shapes are comprised of an undoped, or lightly doped amorphous silicon layer, placed as the outside layer, while a heavily doped amorphous silicon layer is used for the inside layer.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: June 15, 1999
    Inventors: Dahcheng Lin, Jung-Ho Chang, Hsi-Chuan Chen
  • Patent number: 5897352
    Abstract: A method for creating a stacked capacitor structure, with increased surface area, needed for high density, DRAM designs, has been developed. A storage node electrode, featuring a top surface of HSG polysilicon lumps, is used for the surface area increase. A feature of this invention is the use of a thin, heavily doped, polysilicon layer, formed on the HSG polysilicon lumps, resulting in improved adhesion between HSG polysilicon lumps and the underlying polysilicon storage node shape. The thin, heavily doped, polysilicon layer also supplies dopant to underlying HSG polysilicon lumps, needed to reduce a capacitor depletion phenomena which can occur if undoped HSG polysilicon lumps are used.
    Type: Grant
    Filed: March 25, 1998
    Date of Patent: April 27, 1999
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Dahcheng Lin, Jung-Ho Chang, Hsi-Chuan Chen
  • Patent number: 5877052
    Abstract: A method for creating stacked capacitor structures, with increased surface area, obtained using storage node electrode structures comprised of an HSG silicon layer, on a heavily doped amorphous silicon layer, both overlying polysilicon storage node shapes, has been developed. A dilute hydrofluoric acid pre-clean procedure is used prior to depositing a heavily doped amorphous silicon layer, on underlying polysilicon storage node shapes. An overlying second amorphous silicon layer is in situ deposited, in the same furnace used for the prior deposition of heavily doped amorphous silicon layer, followed by an in situ seeding/annealing procedure, converting the second amorphous silicon layer to an HSG silicon layer. This invention features the use of the acid pre-clean, to improve adhesion of the heavily doped amorphous silicon layer, to underlying polysilicon storage node shapes.
    Type: Grant
    Filed: June 11, 1998
    Date of Patent: March 2, 1999
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Dahcheng Lin, Jung-Ho Chang, Hsi-Chuan Chen, Kuo-Shu Tseng