Abstract: A synchronizing circuit translates signals in a slow clock domain into a fast clock domain. The frequency of the slow clock is a submultiple of the fast clock frequency. A synchronizing pulse signal is developed at the frequency of the slow clock, but is phase synchronized to the fast clock. The synchronizing pulse signal is employed to gate the signal in the slow clock domain so that it is synchronized in the fast clock domain. In a system where the ratio between the fast clock frequency and slow clock frequency is determined by a frequency divisor signal, a snooping circuit is employed to capture the frequency divisor signal to achieve rapid synchronization between the clock domains.

Abstract: A bridge circuit adapted to be associated with a PCI and a secondary bus circuits which bridge circuit includes circuitry for storing an indication that a particular PCI bus master has attempted an access of the secondary bus and has been forced to retry that access, circuitry for masking any retry until the bus is again available, and circuitry for providing an interval during which a retrying PCI bus master is guaranteed access to the secondary bus in favor of a bus master on the secondary bus after the bus is relinquished so that a sequence of retry operations causing a loss of bandwidth on the PCI bus is not generated.

Abstract: A computer system comprises a direct memory access (DMA) transfer unit and a plurality of DMA devices coupled by an external bus. The DMA transfer unit effectuates DMA transfers for the plurality of DMA devices. The DMA transfer unit contains a DMA controller, a bus arbiter, and a bus controller. The DMA controller and the bus controller generate a two-clock cycle DMA transfer. To effectuate a two-clock cycle DMA transfer, a requesting DMA device sets-up a DMA transfer with the DMA controller such that a DACK# signal is asserted during a first clock period. During a second clock period, the DMA controller sets-up the memory address. During a third clock period, the bus controller transitions a command signal on the external bus. Upon assertion of the command signal, valid data is asserted on the external bus. For demand and block mode operations, additional DMA transfers are executed in a two-clock cycle DMA transfer. The DMA controller and the bus controller also generate a three-clock cycle DMA transfer.

Abstract: A bridge circuit providing for efficient data transfer between a first bus and a second bus in a computer system. The bridge circuit receives an address indicating a memory location storing a data segment requested to be transferred from the first bus to the second bus. Fetch circuitry fetches the requested data from the first bus and prefetches one or more additional data segments stored in memory locations sequentially following the memory location storing the requested data. The prefetched data segments are stored in a buffer for immediate access by subsequent data transfer requests. Supply circuitry transfers each data segment from the buffer to the second bus in response to receiving an address corresponding to the particular data segment on the address input circuitry.

Abstract: A computer system comprising programmable I/O recovery includes a device selection unit, programmable I/O recovery time registers, and a decrementer for specifying I/O recovery times for a plurality of I/O peripheral components. The programmable I/O recovery time registers contain time values, and the time values are programmable by the user of the computer system. The computer system interfaces the I/O peripheral components on an external bus through a plurality of bus cycle signals generated by cycle generation logic. For each I/O bus cycle on the external bus, the device selection unit identifies the I/O device involved in the I/O bus cycle. The device selection unit selects a time value from the programmable I/O recovery time registers corresponding to the I/O device identified, and loads the time value selected in the decrementer. Upon termination of the bus cycle, the device selection unit generates a cycle start signal to enable counting in the decrementer.

Abstract: A latching mechanism captures an address transmitted on a multiplexed address/data bus and preserves it for the full bus cycle. A transparent latch with a multiplexed feedback path allows the address to be quickly captured and decoded. An additional multiplexer and latch cooperate with the first mentioned latch to keep the address stable for a sufficient time to allow latching by slower memory elements. Additional elements are provided to automatically increment the address for multiple data burst operation.