Patents by Inventor Dai-De WEI

Dai-De WEI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11538195
    Abstract: A method for processing image data and a system thereof are provided. The method is operated in the system including an encoding system and a decoding system. In the decoding system, multiple image data packages are received from the encoding system. The image data packages include multiple encoded data that are formed by encoding the pixels of an image and the pixels are beforehand rearranged according to an arrangement order. The arrangement order is exemplarily made based on the quantity of encoding circuits of the encoding system. In the decoding system, the encoded data received from the encoding system are sequentially stored in a memory according to the arrangement order. The decoding circuits start to decode the encoded data from an initial code synchronously for enhancing decoding performance. The method can be applied to decoding of high resolution images. The image is reproduced after the decoding process.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: December 27, 2022
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Wen-Yi Mao, Jin-Fu Huang, Dai-De Wei
  • Patent number: 11353509
    Abstract: A digital circuit robustness verification method is provided that includes the following steps. An internal storage circuit and an external storage circuit corresponding to a circuit under test are set to store a plurality of random values and a configuration of the circuit under test for performing a predetermined function is set by a processing circuit. A driving signal corresponding to the predetermined function is transmitted to the circuit under test by a previous stage circuit, such that the circuit under test executes the predetermined function to further generate an output signal. The determination as to whether the output signal is correct or not is made by a next stage circuit, and the circuit under test is determined to pass a robustness verification when the output signal is correct.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: June 7, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Wen-Yi Mao, Jin-Fu Huang, Dai-De Wei, Yong-Bin Cao
  • Publication number: 20210166430
    Abstract: A method for processing image data and a system thereof are provided. The method is operated in the system including an encoding system and a decoding system. In the decoding system, multiple image data packages are received from the encoding system. The image data packages include multiple encoded data that are formed by encoding the pixels of an image and the pixels are beforehand rearranged according to an arrangement order. The arrangement order is exemplarily made based on the quantity of encoding circuits of the encoding system. In the decoding system, the encoded data received from the encoding system are sequentially stored in a memory according to the arrangement order. The decoding circuits start to decode the encoded data from an initial code synchronously for enhancing decoding performance. The method can be applied to decoding of high resolution images. The image is reproduced after the decoding process.
    Type: Application
    Filed: November 23, 2020
    Publication date: June 3, 2021
    Inventors: WEN-YI MAO, JIN-FU HUANG, DAI-DE WEI
  • Publication number: 20210072314
    Abstract: A digital circuit robustness verification method is provided that includes the following steps. An internal storage circuit and an external storage circuit corresponding to a circuit under test are set to store a plurality of random values and a configuration of the circuit under test for performing a predetermined function is set by a processing circuit. A driving signal corresponding to the predetermined function is transmitted to the circuit under test by a previous stage circuit, such that the circuit under test executes the predetermined function to further generate an output signal. The determination as to whether the output signal is correct or not is made by a next stage circuit, and the circuit under test is determined to pass a robustness verification when the output signal is correct.
    Type: Application
    Filed: August 25, 2020
    Publication date: March 11, 2021
    Inventors: Wen-Yi MAO, Jin-Fu HUANG, Dai-De WEI, Yong-Bin CAO