Patents by Inventor Dai-Geun Kim
Dai-Geun Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7942506Abstract: An inkjet printer head includes a substrate, an insulating layer having a groove and disposed on the substrate, a heating member having a concavely curved upper surface and disposed on an upper portion of the groove, an electrode to make contact with the heating member to apply electric current to the heating member, a chamber layer disposed on the heating member, and a nozzle layer having one or more nozzles and disposed on the chamber layer. According to the inkjet printer head, the heating member has a curved structure to increase a length of the heating member, so that resistance of the heating member can be increased. Thus, the heating member can stably operate regardless of current variation applied thereto, and the printing work can be performed.Type: GrantFiled: April 30, 2008Date of Patent: May 17, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sung Joon Park, Tae-Jin Kim, Young Hye Park, Dai Geun Kim
-
Patent number: 7564092Abstract: A flash memory device having a split gate that can prevent an active region and a floating gate electrode from being misaligned, and a method of manufacturing the same, includes sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate, forming an isolation layer in a predetermined region of the semiconductor substrate where the floating gate conductive layer is formed, and defining an active region. Then, a local oxide layer is formed by oxidizing a predetermined part of the floating gate conductive layer on the active region. A floating gate electrode structure is formed by patterning the floating gate conductive layer using the local oxide layer.Type: GrantFiled: August 14, 2006Date of Patent: July 21, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Eui-youl Ryu, Chul-soon Kwon, Jin-woo Kim, Yong-hee Kim, Dai-geun Kim, Joo-chan Kim
-
Publication number: 20090027450Abstract: An inkjet print head and a manufacturing method thereof capable of simplifying a manufacturing process without performing an additional process to form a heater layer that includes a substrate, a heating element stacked on the substrate to heat the ink, a transistor having a gate electrode to drive the heating element, a chamber layer to form an ink chamber filled with the ink above the heating element, and a nozzle layer stacked on the chamber layer to form a nozzle to eject the ink, wherein the gate electrode and the heating element include a metal silicide film formed through a salicide process.Type: ApplicationFiled: May 8, 2008Publication date: January 29, 2009Applicant: Samsung Electronics Co., LtdInventors: Sung Joon PARK, Tae Jin Kim, Dai Geun Kim, Jeong Wuk Han
-
Publication number: 20090009562Abstract: An inkjet printer head includes a substrate, an insulating layer having a groove and disposed on the substrate, a heating member having a concavely curved upper surface and disposed on an upper portion of the groove, an electrode to make contact with the heating member to apply electric current to the heating member, a chamber layer disposed on the heating member, and a nozzle layer having one or more nozzles and disposed on the chamber layer. According to the inkjet printer head, the heating member has a curved structure to increase a length of the heating member, so that resistance of the heating member can be increased. Thus, the heating member can stably operate regardless of current variation applied thereto, and the printing work can be performed.Type: ApplicationFiled: April 30, 2008Publication date: January 8, 2009Applicant: Samsung Electronics Co., LtdInventors: Sung Joon PARK, Tae-Jin Kim, Young Hye Park, Dai Geun Kim
-
Patent number: 7195933Abstract: A semiconductor device having a measuring pattern that enhances measuring reliability and a method of measuring the semiconductor device using the measuring pattern. The semiconductor device includes a semiconductor substrate having a chip area in which an integrated circuit is formed, and a scribe area surrounding the chip area. The semiconductor device also includes a measuring pattern formed in the scribe area and having a surface sectional area to include a beam area in which measuring beams are projected, and a dummy pattern formed in the measuring pattern to reduce the surface sectional area of the measuring pattern. The surface sectional area of the dummy pattern occupies from approximately 5% to approximately 15% of a surface sectional area of the beam area.Type: GrantFiled: June 21, 2005Date of Patent: March 27, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Wook Park, Jae-Min Yu, Chul-Soon Kwon, Jin-Woo Kim, Jae-Hyun Park, Yong-Hee Kim, Don-Woo Lee, Dai-Geun Kim, Joo-Chan Kim, Kook-Min Kim, Eui-Youl Ryu
-
Patent number: 7183154Abstract: Nonvolatile memory cells having a split gate structure and methods of fabricating the same are provided. The nonvolatile memory cells include active regions defined at a predetermined region of a semiconductor substrate. A portion of each of the active regions is etched to form a cell trench region. Insulated floating gates are disposed on a pair of sidewalls parallel with the direction that crosses the active region. A source region is disposed at a bottom surface of the cell trench region. A gap region between the floating gates is filled with a common source line electrically connected to the source region. The common source line is extended along the direction that crosses the active regions. The active regions, which are adjacent to the floating gates, are covered with word lines parallel with the common source line. Drain regions are disposed in the active regions adjacent to the word lines. The drain regions are electrically connected to bit lines that cross over the word lines.Type: GrantFiled: November 4, 2004Date of Patent: February 27, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Woo Kim, Dong-Jun Kim, Min-Soo Cho, Dai-Geun Kim
-
Patent number: 7180124Abstract: Nonvolatile memory cells having a split gate structure and methods of fabricating the same are provided. The nonvolatile memory cells include active regions defined at a predetermined region of a semiconductor substrate. A portion of each of the active regions is etched to form a cell trench region. Insulated floating gates are disposed on a pair of sidewalls parallel with the direction that crosses the active region. A source region is disposed at a bottom surface of the cell trench region. A gap region between the floating gates is filled with a common source line electrically connected to the source region. The common source line is extended along the direction that crosses the active regions. The active regions, which are adjacent to the floating gates, are covered with word lines parallel with the common source line. Drain regions are disposed in the active regions adjacent to the word lines. The drain regions are electrically connected to bit lines that cross over the word lines.Type: GrantFiled: November 4, 2004Date of Patent: February 20, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Woo Kim, Dong-Jun Kim, Min-Soo Cho, Dai-Geun Kim
-
Publication number: 20070026613Abstract: A flash memory device having a split gate that can prevent an active region and a floating gate electrode from being misaligned, and a method of manufacturing the same, includes sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate, forming an isolation layer in a predetermined region of the semiconductor substrate where the floating gate conductive layer is formed, and defining an active region. Then, a local oxide layer is formed by oxidizing a predetermined part of the floating gate conductive layer on the active region. A floating gate electrode structure is formed by patterning the floating gate conductive layer using the local oxide layer.Type: ApplicationFiled: August 14, 2006Publication date: February 1, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eui-youl Ryu, Chul-soon Kwon, Jin-woo Kim, Yong-hee Kim, Dai-geun Kim, Joo-chan Kim
-
Patent number: 7094646Abstract: A flash memory device having a split gate that can prevent an active region and a floating gate electrode from being misaligned, and a method of manufacturing the same, includes sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate, forming an isolation layer in a predetermined region of the semiconductor substrate where the floating gate conductive layer is formed, and defining an active region. Then, a local oxide layer is formed by oxidizing a predetermined part of the floating gate conductive layer on the active region. A floating gate electrode structure is formed by patterning the floating gate conductive layer using the local oxide layer.Type: GrantFiled: May 3, 2005Date of Patent: August 22, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Eui-youl Ryu, Chul-soon Kwon, Jin-woo Kim, Yong-hee Kim, Dai-geun Kim, Joo-chan Kim
-
Publication number: 20060001077Abstract: In a split gate type flash memory device, and a method of manufacturing the same, the device includes a memory cell array having a memory cell uniquely determined by a contact of a corresponding bit line and a corresponding word line, a floating gate formed on a semiconductor substrate to constitute the memory cell, the floating gate having a horizontal surface parallel to a main surface of the substrate, a vertical surface perpendicular to the main surface of the substrate, and a curved surface extending between the horizontal and vertical surfaces, a control gate formed over the curved surface of the floating gate in an area defined by an angle range of less than 90° between an extension line of the horizontal surface and an extension line of the vertical surface, and source and drain regions formed in an active region of the substrate.Type: ApplicationFiled: June 15, 2005Publication date: January 5, 2006Inventors: Eui-youl Ryu, Chul-soon Kwon, Jin-woo Kim, Yong-hee Kim, Dai-geun Kim, Joo-chan Kim
-
Publication number: 20050250282Abstract: A flash memory device having a split gate that can prevent an active region and a floating gate electrode from being misaligned, and a method of manufacturing the same, includes sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate, forming an isolation layer in a predetermined region of the semiconductor substrate where the floating gate conductive layer is formed, and defining an active region. Then, a local oxide layer is formed by oxidizing a predetermined part of the floating gate conductive layer on the active region. A floating gate electrode structure is formed by patterning the floating gate conductive layer using the local oxide layer.Type: ApplicationFiled: May 3, 2005Publication date: November 10, 2005Inventors: Eui-youl Ryu, Chul-soon Kwon, Jin-woo Kim, Yong-hee Kim, Dai-geun Kim, Joo-chan Kim
-
Publication number: 20050230786Abstract: A semiconductor device having a measuring pattern that enhances measuring reliability and a method of measuring the semiconductor device using the measuring pattern. The semiconductor device includes a semiconductor substrate having a chip area in which an integrated circuit is formed, and a scribe area surrounding the chip area. The semiconductor device also includes a measuring pattern formed in the scribe area and having a surface sectional area to include a beam area in which measuring beams are projected, and a dummy pattern formed in the measuring pattern to reduce the surface sectional area of the measuring pattern. The surface sectional area of the dummy pattern occupies from approximately 5% to approximately 15% of a surface sectional area of the beam area.Type: ApplicationFiled: June 21, 2005Publication date: October 20, 2005Inventors: Sang-Wook Park, Jae-Min Yu, Chul-Soon Kwon, Jin-Woo Kim, Jae-Hyun Park, Yong-Hee Kim, Don-Woo Lee, Dai-Geun Kim, Joo-Chan Kim, Kook-Min Kim, Eui-Youl Ryu
-
Patent number: 6924505Abstract: A semiconductor device having a measuring pattern that enhances measuring reliability and a method of measuring the semiconductor device using the measuring pattern. The semiconductor device includes a semiconductor substrate having a chip area in which an integrated circuit is formed, and a scribe area surrounding the chip area. The semiconductor device also includes a measuring pattern formed in the scribe area and having a surface sectional area to include a beam area in which measuring beams are projected, and a dummy pattern formed in the measuring pattern to reduce the surface sectional area of the measuring pattern. The surface sectional area of the dummy pattern occupies from approximately 5% to approximately 15% of a surface sectional area of the beam area.Type: GrantFiled: June 2, 2004Date of Patent: August 2, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Wook Park, Jae-Min Yu, Chul-Soon Kwon, Jin-Woo Kim, Jae-Hyun Park, Yong-Hee Kim, Don-Woo Lee, Dai-Geun Kim, Joo-Chan Kim, Kook-Min Kim, Eui-Youl Ryu
-
Publication number: 20050064655Abstract: Nonvolatile memory cells having a split gate structure and methods of fabricating the same are provided. The nonvolatile memory cells include active regions defined at a predetermined region of a semiconductor substrate. A portion of each of the active regions is etched to form a cell trench region. Insulated floating gates are disposed on a pair of sidewalls parallel with the direction that crosses the active region. A source region is disposed at a bottom surface of the cell trench region. A gap region between the floating gates is filled with a common source line electrically connected to the source region. The common source line is extended along the direction that crosses the active regions. The active regions, which are adjacent to the floating gates, are covered with word lines parallel with the common source line. Drain regions are disposed in the active regions adjacent to the word lines. The drain regions are electrically connected to bit lines that cross over the word lines.Type: ApplicationFiled: November 4, 2004Publication date: March 24, 2005Inventors: Jin-Woo Kim, Dong-Jun Kim, Min-Soo Cho, Dai-Geun Kim
-
Publication number: 20050056880Abstract: Nonvolatile memory cells having a split gate structure and methods of fabricating the same are provided. The nonvolatile memory cells include active regions defined at a predetermined region of a semiconductor substrate. A portion of each of the active regions is etched to form a cell trench region. Insulated floating gates are disposed on a pair of sidewalls parallel with the direction that crosses the active region. A source region is disposed at a bottom surface of the cell trench region. A gap region between the floating gates is filled with a common source line electrically connected to the source region. The common source line is extended along the direction that crosses the active regions. The active regions, which are adjacent to the floating gates, are covered with word lines parallel with the common source line. Drain regions are disposed in the active regions adjacent to the word lines. The drain regions are electrically connected to bit lines that cross over the word lines.Type: ApplicationFiled: November 4, 2004Publication date: March 17, 2005Inventors: Jin-Woo Kim, Dong-Jun Kim, Min-Soo Cho, Dai-Geun Kim
-
Patent number: 6867082Abstract: Nonvolatile memory cells having a split gate structure and methods of fabricating the same are provided. The nonvolatile memory cells include active regions defined at a predetermined region of a semiconductor substrate. A portion of each of the active regions is etched to form a cell trench region. Insulated floating gates are disposed on a pair of sidewalls parallel with the direction that crosses the active region. A source region is disposed at a bottom surface of the cell trench region. A gap region between the floating gates is filled with a common source line electrically connected to the source region. The common source line is extended along the direction that crosses the active regions. The active regions, which are adjacent to the floating gates, are covered with word lines parallel with the common source line. Drain regions are disposed in the active regions adjacent to the word lines. The drain regions are electrically connected to bit lines that cross over the word lines.Type: GrantFiled: May 12, 2004Date of Patent: March 15, 2005Assignee: Samsung Electronics Co., LTDInventors: Jin-Woo Kim, Dong-Jun Kim, Min-Soo Cho, Dai-Geun Kim
-
Publication number: 20050035433Abstract: A semiconductor device having a measuring pattern that enhances measuring reliability and a method of measuring the semiconductor device using the measuring pattern. The semiconductor device includes a semiconductor substrate having a chip area in which an integrated circuit is formed, and a scribe area surrounding the chip area. The semiconductor device also includes a measuring pattern formed in the scribe area and having a surface sectional area to include a beam area in which measuring beams are projected, and a dummy pattern formed in the measuring pattern to reduce the surface sectional area of the measuring pattern. The surface sectional area of the dummy pattern occupies from approximately 5% to approximately 15% of a surface sectional area of the beam area.Type: ApplicationFiled: June 2, 2004Publication date: February 17, 2005Inventors: Sang-Wook Park, Jae-Min Yu, Chul-Soon Kwon, Jin-Woo Kim, Jae-Hyun Park, Yong-Hee Kim, Don-Woo Lee, Dai-Geun Kim, Joo-Chan Kim, Kook-Min Kim, Eui-Youl Ryu
-
Publication number: 20040207005Abstract: Nonvolatile memory cells having a split gate structure and methods of fabricating the same are provided. The nonvolatile memory cells include active regions defined at a predetermined region of a semiconductor substrate. A portion of each of the active regions is etched to form a cell trench region. Insulated floating gates are disposed on a pair of sidewalls parallel with the direction that crosses the active region. A source region is disposed at a bottom surface of the cell trench region. A gap region between the floating gates is filled with a common source line electrically connected to the source region. The common source line is extended along the direction that crosses the active regions. The active regions, which are adjacent to the floating gates, are covered with word lines parallel with the common source line. Drain regions are disposed in the active regions adjacent to the word lines. The drain regions are electrically connected to bit lines that cross over the word lines.Type: ApplicationFiled: May 12, 2004Publication date: October 21, 2004Applicant: SAMSUNG ELECTRONICS CO., LTDInventors: Jin-Woo Kim, Dong-Jun Kim, Min-Soo Cho, Dai-Geun Kim
-
Patent number: 6800525Abstract: The method of manufacturing a split gate flash memory device includes the steps of (a) providing a semiconductor substrate of a conductivity type opposite to that of a first junction region; (b) sequentially forming a first dielectric film, a first conductive film, a second dielectric film and a third dielectric film on an overall upper face of the substrate; (c) etching the third dielectric film by a given thickness so as to expose the second dielectric film; (d) removing the exposed second dielectric film, and eliminating the remaining third dielectric film; (e) etching the first conductive film and the second dielectric film by a given thickness so as to partially expose the first conductive line and the first conductive film; (f) forming a fourth dielectric film on a portion of the exposed first conductive line and first conductive film; (g) eliminating the remaining second dielectric film remained, and exposing the first conductive film provided in a lower part thereof; and (h) etching the first dielectrType: GrantFiled: July 31, 2003Date of Patent: October 5, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Eui-Youl Ryu, Jae-Min Yu, Jin-Woo Kim, Jae-Hyun Park, Yong-Hee Kim, Don-Woo Lee, Dai-Geun Kim, Sag-Wook Park, Joo-Chan Kim, Kook-Min Kim, Min-Soo Cho, Chul-Soon Kwon
-
Patent number: 6753571Abstract: Nonvolatile memory cells having a split gate structure and methods of fabricating the same are provided. The nonvolatile memory cells include active regions defined at a predetermined region of a semiconductor substrate. A portion of each of the active regions is etched to form a cell trench region. Insulated floating gates are disposed on a pair of sidewalls parallel with the direction that crosses the active region. A source region is disposed at a bottom surface of the cell trench region. A gap region between the floating gates is filled with a common source line electrically connected to the source region. The common source line is extended along the direction that crosses the active regions. The active regions, which are adjacent to the floating gates, are covered with word lines parallel with the common source line. Drain regions are disposed in the active regions adjacent to the word lines. The drain regions are electrically connected to bit lines that cross over the word lines.Type: GrantFiled: March 28, 2003Date of Patent: June 22, 2004Assignee: Samsung Electronics Co., LTDInventors: Jin-Woo Kim, Dong-Jun Kim, Min-Soo Cho, Dai-Geun Kim