Abstract: To provide a semiconductor device with a tolerant buffer capable of protecting the internal circuit even when the power supply potential is turned 0 [V]. In the semiconductor device, the protection voltage generating circuit 100 generates the larger of the divided voltage and the power supply voltage Vdd obtained by dividing the voltage padv applied to the pad 4 as the protection voltage protectv. The first protection circuit 200 for protecting the internal logic circuit 2A,2B and the output buffer 10 and the second protection circuit 300 for protecting the input buffer 20 operate protectv this protection voltage.

Abstract: To provide a semiconductor device with a tolerant buffer capable of protecting the internal circuit even when the power supply potential is turned 0 [V]. In the semiconductor device, the protection voltage generating circuit 100 generates the larger of the divided voltage and the power supply voltage Vdd obtained by dividing the voltage padv applied to the pad 4 as the protection voltage protectv. The first protection circuit 200 for protecting the internal logic circuit 2A,2B and the output buffer 10 and the second protection circuit 300 for protecting the input buffer 20 operate protectv this protection voltage.

Abstract: The present invention provides a level shift circuit and a semiconductor device capable of extending a power supply potential range in which the level shift operation can be performed. A level shift circuit includes amplitude amplifying circuits AMPt1, AMPb1, and a sublevel shift circuit SLSC1. The amplitude amplifying circuits AMPt1, AMPb1 are supplied with a reference power supply potential GND and an external power supply potential VDD2 and, in response to an input signal (INT, INB) of an internal power supply voltage amplitude (VDD1 (<VDD2) amplitude), output signals SND1, SND2 with an amplitude larger than the VDD1 amplitude and smaller than the external power supply voltage amplitude (VDD2 amplitude). The sublevel shift circuit SLSC1 is supplied with the reference power supply potential GND and the external power supply potential VDD2, and outputs an output signal (OUT, OUTB) of the VDD2 amplitude in response to the signals SND1, SND2.

Abstract: An input circuit includes an inverter, a first path control circuit and a second path control circuit. An input of the inverter is connected with a first node. A target inversion potential is higher than an inversion potential of the inverter. The first path control circuit electrically connects an input terminal and the first node when the input potential is higher than the target inversion potential, and blocks off an electrical connection between the input terminal and the first node when the input potential is lower than the target inversion potential. The second path control circuit electrically connects a ground terminal and the first node when the input potential is lower than a second inversion potential which is lower than the target inversion potential and blocks off the electrical connection between the ground terminal and the first node when the input potential is higher than the second inversion potential.