Patents by Inventor Dai Shinozaki
Dai Shinozaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9607922Abstract: A semiconductor device includes a semiconductor chip which can be a heat-generating semiconductor chip or a semiconductor relay substrate in which an integrated circuit or wiring is built in. A sintered-silver-coated film is adhered on a surface layer part of the semiconductor substrate, interposed by a silicon oxide film. A heat-dissipating fin (heat sink), which may be copper or aluminum, is bonded on the sintered-silver-coated film, interposed by an adhesive layer.Type: GrantFiled: March 3, 2014Date of Patent: March 28, 2017Assignee: TANAKA KIKINZOKU KOGYO K.K.Inventors: Kenji Matsuda, Dai Shinozaki, Yuichi Makita, Hitoshi Kubo, Yusuke Ohshima, Hidekazu Matsuda, Junichi Taniuchi
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Publication number: 20160049350Abstract: A semiconductor device includes a semiconductor chip which can be a heat-generating semiconductor chip or a semiconductor relay substrate in which an integrated circuit or wiring is built in. A sintered-silver-coated film is adhered on a surface layer part of the semiconductor substrate, interposed by a silicon oxide film. A heat-dissipating fin (heat sink), which may be copper or aluminum, is bonded on the sintered-silver-coated film, interposed by an adhesive layer.Type: ApplicationFiled: March 3, 2014Publication date: February 18, 2016Inventors: Kenji MATSUDA, Dai SHINOZAKI, Yuichi MAKITA, Hitoshi KUBO, Yusuke OHSHIMA, Hidekazu MATSUDA, Junichi TANIUCHI
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Publication number: 20140239484Abstract: In a method for forming a sintered silver coating film, for use as a heat spreader, on a semiconductor substrate or a semiconductor package, a coating film of an ink or paste containing silver nanoparticles is formed on one surface of the semiconductor substrate or the substrate package. Further, the coating film is sintered by heating the coating film under an atmosphere of a humidity of 30% to 50% RH (30° C.) by a ventilation oven.Type: ApplicationFiled: February 19, 2014Publication date: August 28, 2014Applicant: Tokyo Electron LimitedInventors: Kenji MATSUDA, Dai SHINOZAKI, Muneo HARADA, Yoshinobu MITANO, Michikazu NAKAMURA, Itaru IIDA, Shinjiro WATANABE
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Patent number: 8749068Abstract: A mounting method of sequentially mounting elements on a substrate includes a mounting process of mounting one element, which is taken out by a take-out part from an accommodating part in which the elements are accommodated, on a first contact region of the surface of the substrate where a liquid is coated. The method further includes a coating process of coating a liquid, by a coating part movably provided together with the take-out part, on a contact region of the surface of the substrate different from the first contact region when the one element is mounted on the first region.Type: GrantFiled: December 24, 2010Date of Patent: June 10, 2014Assignee: Tokyo Electron LimitedInventors: Michikazu Nakamura, Masahiko Sugiyama, Dai Shinozaki, Naoki Akiyama
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Patent number: 8471585Abstract: A yield and productivity of a semiconductor module are improved. A sheet having electrical conductivity is fixed to a main surface of a semiconductor substrate on which a plurality of semiconductor devices having a surface structure and a rear surface electrode are arranged. The semiconductor substrate is divided into semiconductor chips on a first support stage in the state where the sheet is fixed to its main surface. The plurality of divided semiconductor chips are mounted on a second support stage via the sheet and further, the plurality of mounted semiconductor chips are continuously subjected to a dynamic characteristic test on the second support stage. The proposed semiconductor device evaluation method permits a fissure growing and propagating from a crack occurring in the dynamic characteristic test of the vertical semiconductor devices to be suppressed, and the yield and productivity of the semiconductor module to be improved.Type: GrantFiled: July 21, 2010Date of Patent: June 25, 2013Assignees: Tokyo Electron Limited, Fuji Electric Systems Co., Ltd.Inventors: Mitsuyoshi Miyazono, Shigekazu Komatsu, Dai Shinozaki, Masahiro Kato, Atsushi Yoshida
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Publication number: 20120291950Abstract: A mounting method of mounting an element on a substrate, includes a first hydrophilization process of hydrophilizing a region on a surface of the substrate where the element is to be joined; a second hydrophilization process of hydrophilizing the surface of the element; a mounting process of mounting the element on a mounting part such that the hydrophilized surface of the element faces upwards; a coating process of coating a liquid on the hydrophilized surface of the element; and an arrangement process of arranging the substrate above the mounting part such that the region on the surface of the substrate where the element is to be joined faces downwards. The method further includes a contact process of bringing the substrate arranged above the mounting part close to the mounting part on which the element is mounted to bring the liquid into contact with the surface of the substrate.Type: ApplicationFiled: December 24, 2010Publication date: November 22, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Masahiko Sugiyama, Michikazu Nakamura, Dai Shinozaki, Naoki Akiyama
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Publication number: 20120292775Abstract: A mounting method of sequentially mounting elements on a substrate includes a mounting process of mounting one element, which is taken out by a take-out part from an accommodating part in which the elements are accommodated, on a first contact region of the surface of the substrate where a liquid is coated. The method further includes a coating process of coating a liquid, by a coating part movably provided together with the take-out part, on a contact region of the surface of the substrate different from the first contact region when the one element is mounted on the first region.Type: ApplicationFiled: December 24, 2010Publication date: November 22, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Michikazu Nakamura, Masahiko Sugiyama, Dai Shinozaki, Naoki Akiyama
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Publication number: 20110050269Abstract: A yield and productivity of a semiconductor module are improved. A sheet having electrical conductivity is fixed to a main surface of a semiconductor substrate on which a plurality of semiconductor devices having a surface structure and a rear surface electrode are arranged. The semiconductor substrate is divided into semiconductor chips on a first support stage in the state where the sheet is fixed to its main surface. The plurality of divided semiconductor chips are mounted on a second support stage via the sheet and further, the plurality of mounted semiconductor chips are continuously subjected to a dynamic characteristic test on the second support stage. The proposed semiconductor device evaluation method permits a fissure growing and propagating from a crack occurring in the dynamic characteristic test of the vertical semiconductor devices to be suppressed, and the yield and productivity of the semiconductor module to be improved.Type: ApplicationFiled: July 21, 2010Publication date: March 3, 2011Applicants: TOKYO ELECTRON LIMITED, FUJI ELECTRIC SYSTEMS CO., LTD.Inventors: Mitsuyoshi Miyazono, Shigekazu Komatsu, Dai Shinozaki, Masahiro Kato, Atsushi Yoshida
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Patent number: 7701241Abstract: A circuit for protecting a DUT is disposed in parallel with a DUT which is supplied with current via wirings and switchable between conducting and non-conducting state. The circuit is switchable between conducting and non-conducing state and switched from non-conducting state to conducting state as the DUT is switched from conducting state to non-conducting state.Type: GrantFiled: March 21, 2007Date of Patent: April 20, 2010Assignee: Tokyo Electron LimitedInventors: Yasunori Kumagai, Dai Shinozaki, Shigekazu Komatsu, Katsuaki Sakamoto
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Patent number: 7586317Abstract: By allowing an electrical conduction between a probe and an electrode by a fritting phenomenon before inspection, simplification of circuit configuration and shortening of inspection time is achieved. A fritting circuit is formed in a probe card of an inspection apparatus for each probe pair consisting of two probes. A capacitor is connected to each fritting circuit. Each fritting circuit is connected in parallel to a power supply circuit having a charging power supply. Each capacitor is charged at one time by the power supply circuit. The probe pair is brought into contact with an electrode of a wafer, and a high-voltage is applied to the probe pair by a power charged in the capacitor, thereby achieving an electrical connection between each probe and the electrode by a fritting phenomenon. Then, an inspection of electrical characteristics is performed by using an electric inspection signal transmitted to each probe.Type: GrantFiled: July 16, 2008Date of Patent: September 8, 2009Assignee: Tokyo Electron LimitedInventors: Shigekazu Komatsu, Dai Shinozaki, Katsuaki Sakamoto
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Publication number: 20090021272Abstract: By allowing an electrical conduction between a probe and an electrode by a fritting phenomenon before inspection, simplification of circuit configuration and shortening of inspection time is achieved. A fritting circuit is formed in a probe card of an inspection apparatus for each probe pair consisting of two probes. A capacitor is connected to each fritting circuit. Each fritting circuit is connected in parallel to a power supply circuit having a charging power supply. Each capacitor is charged at one time by the power supply circuit. The probe pair is brought into contact with an electrode of a wafer, and a high-voltage is applied to the probe pair by a power charged in the capacitor, thereby achieving an electrical connection between each probe and the electrode by a fritting phenomenon. Then, an inspection of electrical characteristics is performed by using an electric inspection signal transmitted to each probe.Type: ApplicationFiled: July 16, 2008Publication date: January 22, 2009Applicant: Tokyo Electron LimitedInventors: Shigekazu Komatsu, Dai Shinozaki, Katsuaki Sakamoto
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Patent number: 7301357Abstract: In an inspection method according to the invention, a plurality of drivers 21 incorporated in a tester 20 apply a fritting voltage to respective electrodes P via first probe pins 11A included in pairs of first and second probe pins 11A and 11B and connected to the respective drivers.Type: GrantFiled: December 9, 2003Date of Patent: November 27, 2007Assignee: Tokyo Electron LimitedInventors: Dai Shinozaki, Shigekazu Komatsu
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Publication number: 20070223156Abstract: A circuit for protecting a DUT is disposed in parallel with a DUT which is supplied with current via wirings and switchable between conducting and non-conducting state. The circuit is switchable between conducting and non-conducing state and switched from non-conducting state to conducting state as the DUT is switched from conducting state to non-conducting state.Type: ApplicationFiled: March 21, 2007Publication date: September 27, 2007Applicant: TOKYO ELECTRON LIMITEDInventors: Yasunori Kumagai, Dai Shinozaki, Shigekazu Komatsu, Katsuaki Sakamoto
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Publication number: 20060061374Abstract: In an inspection method according to the invention, a plurality of drivers 21 incorporated in a tester 20 apply a fritting voltage to respective electrodes P via first probe pins 11A included in pairs of first and second probe pins 11A and 11B and connected to the respective drivers.Type: ApplicationFiled: December 9, 2003Publication date: March 23, 2006Inventors: Dai Shinozaki, Shigekazu Komatsu