Patents by Inventor Dai Yamamoto

Dai Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8335313
    Abstract: When processing a data conversion function of a MISTY structure, such as the FO function of MISTY1, the logical calculation result t3 of the exclusive OR 614 of the process result of the FI function 602 of the MISTY structure in the second stage and a logical calculation result t1 of an exclusive OR 612 of the MISTY structure in the first stage is not stored in a register. The logical calculation result t3 and the logical calculation result of respective exclusive OR 642 and 643 are subject to a direct exclusive OR with the respective exclusive OR 642 and 643.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: December 18, 2012
    Assignee: Fujitsu Limited
    Inventors: Jun Yajima, Dai Yamamoto, Kouichi Itoh
  • Patent number: 8295479
    Abstract: In a MISTY1 FI function, an exclusive OR to which a round key KIij2 is inputted is arranged between an exclusive OR arranged on a 9-bit critical path in a first MISTY structure and a zero-extend conversion connected to the branching point of a 7-bit right system data path. Then, a 9-bit round key KIij1 is truncate-converted to seven bits, the exclusive OR of the seven bits and the round key KIij1 is calculated by an exclusive OR and the calculation result is inputted to an exclusive OR arranged on the right system data path in the second stage MISTY structure.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: October 23, 2012
    Assignee: Fujitsu Limited
    Inventors: Dai Yamamoto, Jun Yajima, Kouichi Itoh
  • Patent number: 8111827
    Abstract: A cryptographic processing apparatus for performing arithmetic operation on an FL function and an FL?1 function in a cryptographic process includes a first arithmetic gate is configured to receive a first input bit string and a first extended key bit string, a first XOR gate configured to receive an output of the first arithmetic gate and a second input bit string, a second arithmetic gate configured to receive an output of the first XOR gate and a second extended key bit string, a second XOR gate configured to receive an output of the second arithmetic gate and the first input bit string, a third arithmetic gate configured to receive an output of the second XOR gate and the first extended key bit string, and a third XOR gate configured to receive an output of the third arithmetic gate and an output of the first XOR gate.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: February 7, 2012
    Assignee: Fujitsu Limited
    Inventors: Dai Yamamoto, Kouichi Itoh
  • Publication number: 20110176673
    Abstract: An encrypting apparatus includes a digest part using a SHA-2 algorithm of which a basic unit of operation is 32*Y (Y=1 or 2) bits. The digest part includes a shift register including a series of registers, and a predetermined number of adders performing an addition operation based on data stored in the shift register. The shift register includes a (32*Y)/X-bit register, where X=2k (k is an integer such that 1?k?4 when Y=1 and 1?k?5 when Y=2). Each of the adders has a data width of (32*Y)/X bits and performs the addition operation in each cycle in which the data stored in the shift register is shifted between the registers with the data width of (32*Y)/X bits.
    Type: Application
    Filed: March 25, 2011
    Publication date: July 21, 2011
    Applicants: Fujitsu Limited, Fujitsu Semiconductor Limited
    Inventors: Dai Yamamoto, Kouichi Itoh, Masayoshi Isobe, Souichi Okada
  • Publication number: 20110075836
    Abstract: An apparatus includes a data storage to store a window table storing a table value with an index value mapped to the table value, the index value having same number of bits as a window width, the table value being a sum of a basic table value and a non-zero table correction value, the basic table value being obtained by multiplying a point G on an elliptic curve. An arithmetic processor generates the index value by reading from a scalar value at a bit position assigned to each bit of the window with the window being shifted, reads the table value from the window table according to the index value, and performs a doubling operation and an addition operation using the read table value. A corrector performs a correction on arithmetic results with a specific correction value responsive to the table correction value.
    Type: Application
    Filed: September 27, 2010
    Publication date: March 31, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Dai YAMAMOTO, Kouichi Itoh
  • Publication number: 20100278332
    Abstract: In a MISTY1 FI function, an exclusive OR to which a round key KIij2 is inputted is arranged between an exclusive OR arranged on a 9-bit critical path in a first MISTY structure and a zero-extend conversion connected to the branching point of a 7-bit right system data path. Then, a 9-bit round key KIij1 is truncate-converted to seven bits, the exclusive OR of the seven bits and the round key KIij1 is calculated by an exclusive OR and the calculation result is inputted to an exclusive OR arranged on the right system data path in the second stage MISTY structure.
    Type: Application
    Filed: July 12, 2010
    Publication date: November 4, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Dai YAMAMOTO, Jun Yajima, Kouichi Itoh
  • Publication number: 20100276309
    Abstract: In a state where liquids are contained in a plurality of liquid container portions which are formed in a first layer and a second layer of a cartridge and which have predetermined volumes determined depending on liquids to be contained, and where the reaction vessel is connected to any one of communicating ports, when pressure is applied to act upon one of the liquid container portions which is communicated with the communicating port connected to the reaction vessel, the atmosphere is supplied to the one liquid container portion through a atmosphere flowing passage communicating with the outside, and the liquid contained in the one liquid container portion is supplied to the reaction vessel. The cartridge is rotated to connect another communicating port to the reaction vessel such that plural liquids are eventually supplied to the reaction vessel.
    Type: Application
    Filed: December 12, 2008
    Publication date: November 4, 2010
    Inventors: Masahiro Murasato, Kazunari Yamada, Dai Yamamoto, Akinobu Oribe, Kousuke Niwa
  • Publication number: 20100278340
    Abstract: When processing a data conversion function of a MISTY structure, such as the FO function of MISTY1, the logical calculation result t3 of the exclusive OR 614 of the process result of the FI function 602 of the MISTY structure in the second stage and a logical calculation result t1 of an exclusive OR 612 of the MISTY structure in the first stage is not stored in a register. The logical calculation result t3 and the logical calculation result of respective exclusive OR 642 and 643 are subject to a direct exclusive OR with the respective exclusive OR 642 and 643.
    Type: Application
    Filed: July 12, 2010
    Publication date: November 4, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Jun YAJIMA, Dai YAMAMOTO, Kouichi ITOH
  • Publication number: 20100232601
    Abstract: An apparatus for executing cryptographic calculation on the basis of an elliptic point on an elliptic curve includes: a memory for storing a first value including a plurality of digits; and a processor for executing a process including: obtaining a second value representing a point on the elliptic curve; calculating output values by using a predetermined equation, each digit of the first value, and the second value; determining whether at least one of the second value and the output values indicates a point of infinity; terminating the calculation when at least one of the second value and the output values indicates the point at infinity; and completing calculation when both the second value and the output values do not indicate the point at infinity, so as to obtain a result of the cryptographic calculation.
    Type: Application
    Filed: January 15, 2010
    Publication date: September 16, 2010
    Applicant: Fujitsu Limited
    Inventors: Kouichi ITOH, Dai Yamamoto, Tetsuya Izu, Masahiko Takenaka, Kazuyoshi Furukawa
  • Publication number: 20100183144
    Abstract: A cipher processing apparatus for arithmetic operations of an FO function and an FL function comprising: an FL function operating unit for generating a 2N-bit output based on a first extension key; a partial function operating unit for generating an N-bit output based on second and third extension keys; an N-bit intermediate register for storing an output of the partial operating unit; a 2N-bit first data register for storing data based on the output of the FL function operating unit; and a controller for making the partial function operating unit perform six cycles, inputting an output of the intermediate register to the FL function operating unit, and storing the data based on the output of the FL function operating unit in the first data register, in a first case in which the FL function uses a result of an arithmetic operation of the FO function.
    Type: Application
    Filed: January 13, 2010
    Publication date: July 22, 2010
    Applicant: Fujitsu Limited
    Inventors: Dai Yamamoto, Kouichi Itoh, Jun Yajima
  • Publication number: 20100183143
    Abstract: A cryptographic processing apparatus for performing arithmetic operation on an FL function and an FL?1 function in a cryptographic process includes a first arithmetic gate is configured to receive a first input bit string and a first extended key bit string, a first XOR gate configured to receive an output of the first arithmetic gate and a second input bit string, a second arithmetic gate configured to receive an output of the first XOR gate and a second extended key bit string, a second XOR gate configured to receive an output of the second arithmetic gate and the first input bit string, a third arithmetic gate configured to receive an output of the second XOR gate and the first extended key bit string, and a third XOR gate configured to receive an output of the third arithmetic gate and an output of the first XOR gate.
    Type: Application
    Filed: November 4, 2009
    Publication date: July 22, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Dai YAMAMOTO, Kouichi Itoh