Patents by Inventor Daichi Dojima

Daichi Dojima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240068958
    Abstract: An object of the present invention is to provide a novel technology capable of evaluating a subsurface damaged layer without destroying a semiconductor substrate. As means for solving this object, the present invention includes a measurement step of causing laser light having penetration characteristics to be incident from a surface of a semiconductor substrate having a subsurface damaged layer under the surface and measuring an intensity of scattered light scattered under the surface, and an evaluation step of evaluating the subsurface damaged layer on the basis of the intensity of the scattered light obtained in the measurement step.
    Type: Application
    Filed: December 9, 2022
    Publication date: February 29, 2024
    Inventors: Tadaaki KANEKO, Daichi DOJIMA, Kazunobu ASAKAWA
  • Publication number: 20240020814
    Abstract: An object of the present invention is to provide a novel technique for evaluating a heat treatment environment. The present invention is a method for evaluating a heat treatment environment, the method comprising an image acquisition step of acquiring an image by making an electron beam incident at an incident angle inclined with respect to a normal line of a {0001} plane of a heat-treated silicon carbide substrate and an environment evaluation step of evaluating a heat treatment environment of the silicon carbide substrate on a basis of on contrast information of the image.
    Type: Application
    Filed: October 27, 2021
    Publication date: January 18, 2024
    Inventors: Tadaaki KANEKO, Daichi DOJIMA
  • Publication number: 20230411225
    Abstract: An object of the present invention is to provide a novel evaluation method suitable for evaluating a SiC substrate having a large diameter. The present invention is a method for evaluating a silicon carbide substrate, the method comprising an image acquisition step of acquiring an image by making an electron beam incident at an incident angle inclined with respect to a normal line of a {0001} plane of a silicon carbide substrate, wherein the incident angle is 10° or less.
    Type: Application
    Filed: October 27, 2021
    Publication date: December 21, 2023
    Inventors: Tadaaki KANEKO, Daichi DOJIMA
  • Publication number: 20230392282
    Abstract: A problem addressed by the present invention is to provide a novel technique with which is possible to suppress the introduction of dislocation into a growth layer. The present invention, which solves the above problem, is a method for producing an aluminum nitride substrate, the method including a processing step for removing part of silicon carbide substrate and forming a pattern that includes a minor angle, and a crystal growth step for forming an aluminum nitride growth layer on the silicon carbide substrate on which the patter has been formed. The present invention is also a method for suppressing the introduction of dislocation into the aluminum nitride growth layer, the method including a processing step for removing part of the silicon carbide substrate and forming a pattern that includes a minor angle before forming a growth layer on a base substrate.
    Type: Application
    Filed: March 30, 2021
    Publication date: December 7, 2023
    Inventors: Tadaaki KANEKO, Daichi DOJIMA, Taku MURAKAWA, Moeko MATSUBARA, Yoshitaka NISHIO
  • Publication number: 20230304186
    Abstract: An object of the present invention is to provide a novel technique capable of manufacturing a large-diameter AlN substrate. The present invention is a method for manufacturing an AlN substrate, including a crystal growth step S30 of forming an AlN layer 20 on a SiC underlying substrate 10 having through holes 11. In addition, the present invention is a method for forming an AlN layer including the through hole formation step S20 of forming the through holes 11 in the SiC underlying substrate 10 before forming the AlN layer 20 on the SiC underlying substrate 10.
    Type: Application
    Filed: March 30, 2021
    Publication date: September 28, 2023
    Inventors: Tadaaki KANEKO, Daichi DOJIMA, Moeko MATSUBARA, Yoshitaka NISHIO
  • Publication number: 20230212785
    Abstract: The problem to be solved by the present invention is to provide a novel technique that can remove a strained layer introduced into an aluminum nitride substrate. In order to solve this problem, the present aluminum nitride substrate manufacturing method involves a strained layer removal step for removing a strained layer in an aluminum nitride substrate by heat treatment of the aluminum nitride substrate in a nitrogen atmosphere. In this way, the present invention can remove a strained layer that has been introduced into an aluminum nitride substrate.
    Type: Application
    Filed: March 30, 2021
    Publication date: July 6, 2023
    Inventors: Tadaaki KANEKO, Daichi DOJIMA, Moeko MATSUBARA, Yoshitaka NISHIO
  • Publication number: 20230203704
    Abstract: An object of the present invention is to provide a novel technique capable of suppressing the occurrence of cracks in the growth layer. The present invention is a method for manufacturing a semiconductor substrate, which includes: an embrittlement processing step S10 of reducing strength of an underlying substrate 10; and a crystal growth step S20 of forming the growth layer 20 on the underlying substrate 10. In addition, the present invention is a method for suppressing the occurrence of cracks in the growth layer 20, and this method includes an embrittlement processing step S10 of reducing the strength of the underlying substrate 10 before forming the growth layer 20 on the underlying substrate 10.
    Type: Application
    Filed: March 30, 2021
    Publication date: June 29, 2023
    Inventors: Tadaaki KANEKO, Daichi DOJIMA
  • Publication number: 20230197486
    Abstract: An object of the present invention is to provide a novel technique capable of suppressing the occurrence of cracks in an AlN layer. The present invention is a method for manufacturing an AlN substrate, the method including: an embrittlement processing step S10 of reducing strength of a SiC underlying substrate 10; and a crystal growth step S20 of forming an AlN layer 20 on the SiC underlying substrate 10. In addition, the present invention is a method for suppressing the occurrence of cracks in the AlN layer 20, the method including the embrittlement processing step S10 of reducing the strength of the SiC underlying substrate 10 before forming the AlN layer 20 on the SiC underlying substrate 10.
    Type: Application
    Filed: March 30, 2021
    Publication date: June 22, 2023
    Inventors: Tadaaki KANEKO, Daichi DOJIMA, Taku MURAKAWA, Moeko MATSUBARA, Yoshitaka NISHIO
  • Publication number: 20230193507
    Abstract: An object of the present invention is to provide a novel technique capable of manufacturing a large-diameter semiconductor substrate. The present invention is a method for manufacturing a semiconductor substrate including a crystal growth step S30 of forming a growth layer 20 on an underlying substrate 10 having through holes 11. In addition, the present invention is a method for forming a growth layer 20 including the through hole formation step S10 of forming through holes 11 in the underlying substrate 10 before forming the growth layer 20 on a surface of the underlying substrate 10.
    Type: Application
    Filed: March 30, 2021
    Publication date: June 22, 2023
    Inventors: Tadaaki KANEKO, Daichi DOJIMA
  • Publication number: 20230197456
    Abstract: The problem to addressed by the present invention is that of providing a novel technique that can remove a strained layer introduced into a silicon carbide substrate by laser processing. The present silicon carbide substrate manufacturing method involves a processing step for performing laser processing to remove part of a silicon carbide substrate by irradiating the silicon carbide substrate with a laser, and a strained layer removal step for removing a strained layer that was introduced in the silicon carbide substrate by the aforementioned processing step involving heat treatment of the silicon carbide substrate. In this way, the present invention, which is a method of removing a strained layer introduced into a silicon carbide substrate by laser processing, involves a strained layer removal step for heat treating the silicon carbide substrate.
    Type: Application
    Filed: March 30, 2021
    Publication date: June 22, 2023
    Inventors: Tadaaki KANEKO, Daichi DOJIMA
  • Publication number: 20230166972
    Abstract: The purpose of the present is to provide a modified AlN source for suppressing downfall defects. This manufacturing method of a modified aluminum nitride source involves a heat treatment step for heat treating an aluminum nitride source and generating an aluminum nitride sintered body.
    Type: Application
    Filed: March 30, 2021
    Publication date: June 1, 2023
    Inventors: Tadaaki KANEKO, Daichi DOJIMA, Moeko MATSUBARA, Yoshitaka NISHIO
  • Publication number: 20230160100
    Abstract: The problem to be solved by the present invention is to provide novel technology capable of suppressing the introduction of displacement to a growth layer. The present invention, which solves the abovementioned problem, pertains to a method for manufacturing a semiconductor substrate, the method including: a processing step for removing a portion of a base substrate and forming a pattern that includes a minor angle; and a crystal growth step for forming a growth layer on the base substrate where the patter has been formed. In addition, the present invention pertains to a method for suppressing the introduction of displacement to a growth layer, the method including a processing step for removing a portion of the base substrate and forming a pattern that includes a minor angle prior to forming the growth layer on the base substrate.
    Type: Application
    Filed: March 30, 2021
    Publication date: May 25, 2023
    Inventors: Tadaaki KANEKO, Daichi DOJIMA
  • Publication number: 20220216116
    Abstract: To provide a new temperature distribution evaluation method, a temperature distribution evaluation device, and a soaking range evaluation method, as the temperature distribution evaluation method which evaluates a temperature distribution of a heating area 40A provided in a heating device 40, the present invention is a temperature distribution evaluation method which, in the heating area 40A, heats a semiconductor substrate 10 and a transmitting and receiving body 20 for transporting a raw material to and from the semiconductor substrate 10, and evaluates a temperature distribution of the heating area 40A on the basis of a substrate thickness variation amount A of the semiconductor substrate 10. Accordingly, temperature distribution evaluation can be implemented for a high temperature area at 1600-2200° C. or the like at which it is hard to evaluate the temperature distribution due to the limit of a thermocouple material.
    Type: Application
    Filed: April 24, 2020
    Publication date: July 7, 2022
    Inventors: Tadaaki KANEKO, Daichi DOJIMA, Koji ASHIDA, Tomoya IHARA
  • Patent number: 11365491
    Abstract: A method includes a graphene precursor formation process of: heating a SiC substrate to sublimate Si atoms in a Si surface of the SiC substrate so that a graphene precursor is formed; and stopping the heating before the graphene precursor is covered with graphene. A SiC substrate to be treated in the graphene precursor formation process is provided with a step including a plurality of molecular layers. The step has a stepped structure in which a molecular layer whose C atom has two dangling bonds is disposed closer to the surface than a molecular layer whose C atom has one dangling bond.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: June 21, 2022
    Assignee: KWANSEI GAKUIN EDUCATIONAL FOUNDATION
    Inventors: Tadaaki Kaneko, Yasunori Kutsuma, Daichi Dojima
  • Publication number: 20210399095
    Abstract: An object of the present invention is to provide a SiC semiconductor substrate having a growth layer with a controlled step height, a manufacturing method thereof, and a manufacturing device thereof. The method includes: a growth process that grows a SiC substrate 10 in a SiC—Si equilibrium vapor pressure environment. In this way, when the SiC substrate 10 is grown in the SiC—Si equilibrium vapor pressure environment, it is possible to provide a SiC semiconductor substrate in which the step height of the growth layer is controlled.
    Type: Application
    Filed: November 5, 2019
    Publication date: December 23, 2021
    Inventors: Tadaaki KANEKO, Koji ASHIDA, Tomoya IHARA, Daichi DOJIMA
  • Publication number: 20210398807
    Abstract: An object of the present invention is to provide a SiC semiconductor substrate capable of reducing a density of basal plane dislocations (BPD) in a growth layer, a manufacturing method thereof, and a manufacturing device thereof. The method includes: a strained layer removal process S10 that removes a strained layer introduced on a surface of a SiC substrate; and an epitaxial growth process S20 that conducts growth under a condition that a terrace width W of the SiC substrate is increased. When a SiC semiconductor substrate is manufactured in such processes, the basal plane dislocations BPD in the growth layer can be reduced, and a yield of a SiC semiconductor device can be improved.
    Type: Application
    Filed: November 5, 2019
    Publication date: December 23, 2021
    Inventors: Tadaaki KANEKO, Koji ASHIDA, Tomoya IHARA, Daichi DOJIMA
  • Publication number: 20190136411
    Abstract: A method includes a graphene precursor formation process of: heating a SiC substrate to sublimate Si atoms in a Si surface of the SiC substrate so that a graphene precursor is formed; and stopping the heating before the graphene precursor is covered with graphene. A SiC substrate to be treated in the graphene precursor formation process is provided with a step including a plurality of molecular layers. The step has a stepped structure in which a molecular layer whose C atom has two dangling bonds is disposed closer to the surface than a molecular layer whose C atom has one dangling bond.
    Type: Application
    Filed: April 27, 2017
    Publication date: May 9, 2019
    Applicant: KWANSEI GAKUIN EDUCATIONAL FOUNDATION
    Inventors: Tadaaki Kaneko, Yasunori Kutsuma, Daichi Dojima