Abstract: A well region in which an insulated gate semiconductor element is formed is a diffusion region, and an impurity concentration of the well region is lower toward its bottom portion. This leads to a problem of increased resistance. Therefore, particularly, an insulated gate semiconductor element having an up-drain structure has a problem of increased on-resistance. A p type well region is formed by stacking two p type impurity regions on one another. The p type impurity regions are allowed to serve as the p type well region by sequentially stacking n type semiconductor layers, on one another, having p type impurities implanted into their surfaces and simultaneously diffusing the impurities by heat treatment. In this way, it is possible to obtain the p type well region in which an impurity concentration sufficient to secure a desired breakdown voltage is maintained approximately uniform up to a desired depth.

Abstract: A well region in which an insulated gate semiconductor element is formed is a diffusion region, and an impurity concentration of the well region is lower toward its bottom portion. This leads to a problem of increased resistance. Therefore, particularly, an insulated gate semiconductor element having an up-drain structure has a problem of increased on-resistance. A p type well region is formed by stacking two p type impurity regions on one another. The p type impurity regions are allowed to serve as the p type well region by sequentially stacking n type semiconductor layers, on one another, having p type impurities implanted into their surfaces and simultaneously diffusing the impurities by heat treatment. In this way, it is possible to obtain the p type well region in which an impurity concentration sufficient to secure a desired breakdown voltage is maintained approximately uniform up to a desired depth.

Abstract: A semiconductor device manufacturing method including forming a conductive layer and a silicon film on a semiconductor substrate including an active region, forming an emitter electrode containing a first impurity on the silicon film above the active region, partially etching the silicon film using the emitter electrode as a mask, forming an insulative film covering the semiconductor substrate and a side wall film covering a side surface of the emitter electrode, introducing a second impurity into the conductive layer and silicon film so that the second impurity reaches the active region to form an impurity region containing the second impurity in parts of the conductive layer and silicon film, and diffusing the first impurity contained in the emitter electrode into the silicon film to form in the silicon film a first region containing the first impurity and a second region free of the first impurity.

Abstract: A semiconductor device manufacturing method including forming a conductive layer and a silicon film on a semiconductor substrate including an active region, forming an emitter electrode containing a first impurity on the silicon film above the active region, partially etching the silicon film using the emitter electrode as a mask, forming an insulative film covering the semiconductor substrate and a side wall film covering a side surface of the emitter electrode, introducing a second impurity into the conductive layer and silicon film so that the second impurity reaches the active region to form an impurity region containing the second impurity in parts of the conductive layer and silicon film, and diffusing the first impurity contained in the emitter electrode into the silicon film to form in the silicon film a first region containing the first impurity and a second region free of the first impurity.

Abstract: A high capacity semiconductor device having a narrowed emitter layer. The semiconductor device includes a collector layer formed on a semiconductor substrate. An SiGe alloy layer is formed on the collector layer. A silicon film is formed on the SiGe layer. An emitter electrode is formed on the silicon film. A side wall film covers the side surface of the emitter electrode. The bottom surface of the emitter electrode is located above the lower surface of the side wall film. Part of the second region of the silicon film is located between the SiGe alloy layer and the side wall film. An impurity region is formed adjacent to the conductive layer. A silicide film is formed along the side surface of the second region, the side surface of the conductive layer, and the surface of the impurity region.

Abstract: A high capacity semiconductor device having a narrowed emitter layer. The semiconductor device includes a collector layer formed on a semiconductor substrate. An SiGe alloy layer is formed on the collector layer. A silicon film is formed on the SiGe layer. An emitter electrode is formed on the silicon film. A side wall film covers the side surface of the emitter electrode. The bottom surface of the emitter electrode is located above the lower surface of the side wall film. Part of the second region of the silicon film is located between the SiGe alloy layer and the side wall film. An impurity region is formed adjacent to the conductive layer. A silicide film is formed along the side surface of the second region, the side surface of the conductive layer, and the surface of the impurity region.

Abstract: A high performance semiconductor device including a silicon oxide film that surrounds an SiGe alloy layer, which functions as a base layer, and an n-type diffusion layer, which functions as an emitter layer. Under a polycrystalline silicon film, the silicon oxide film extends over a boundary between an active region and an element isolation film. After a flat interlayer dielectric is formed, a lead wire is connected to a silicide film located above the isolation film.