Patents by Inventor Daigo HAYASHI

Daigo HAYASHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250037909
    Abstract: An electronic component that can secure a creepage distance between electrode terminals has a structure in which an upper portion having a rectangular shape in plan view and a predetermined thickness, a housing portion formed at the center on an undersurface side of the upper portion to house a resistance element, and first, second, and third protruding portions, each of which extends in a vertical direction from the undersurface side of the upper portion to serve as a leg portion, are formed. A concave portion having a predetermined depth is formed between the first and third protruding portions and between the second and third protruding portions on the undersurface side of the upper portion, such that the concave portion extends from one side in a widthwise direction on the undersurface side to the other side through the housing portion to secure a long creepage distance between electrode terminals.
    Type: Application
    Filed: October 31, 2022
    Publication date: January 30, 2025
    Inventors: Kyohei MIYASHITA, Mizuki UCHIMORI, Daigo HAYASHI
  • Publication number: 20240053970
    Abstract: When a counter circuit that repeatedly counts a loop variable, an accumulator variable, or the like is configured by a programmable device, a processing delay occurs. The processor comprises an array of programmable logic and at least one dedicated counter circuit for counting variables that are repeatedly modified.
    Type: Application
    Filed: June 12, 2023
    Publication date: February 15, 2024
    Inventors: Takao TOI, Kengo NISHINO, Daigo HAYASHI
  • Patent number: 11456094
    Abstract: A highly reliable surface-mounted resistor, which prevents a problem of disconnection between an electrode and a terminal of a chip resistor when heating during mounting, is disclosed. The surface-mounted resistor includes a chip resistor comprising a plate-shaped substrate, a resistance body formed on an upper surface of the substrate, and an electrode connected the resistance body and drawn from the upper surface of the substrate to a lower surface via an end surface, a plate-shaped lead terminal connected to the electrode of the chip resistor, the plate-shaped lead terminal being fixed to the electrode of the substrate on the lower surface side, and an exterior member covering an entire chip resistor and a part of the lead terminal.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: September 27, 2022
    Assignee: KOA CORPORATION
    Inventors: Daigo Hayashi, Jun Ito, Yuko Tezuka
  • Publication number: 20210280343
    Abstract: A highly reliable surface-mounted resistor, which prevents a problem of disconnection between an electrode and a terminal of a chip resistor when heating during mounting, is disclosed. The surface-mounted resistor includes a chip resistor comprising a plate-shaped substrate, a resistance body formed on an upper surface of the substrate, and an electrode connected the resistance body and drawn from the upper surface of the substrate to a lower surface via an end surface, a plate-shaped lead terminal connected to the electrode of the chip resistor, the plate-shaped lead terminal being fixed to the electrode of the substrate on the lower surface side, and an exterior member covering an entire chip resistor and a part of the lead terminal.
    Type: Application
    Filed: February 16, 2021
    Publication date: September 9, 2021
    Applicant: KOA CORPORATION
    Inventors: Daigo Hayashi, Jun Ito, Yuko Tezuka
  • Patent number: 10373684
    Abstract: A semiconductor device includes an N number of sub-blocks each of including a memory cell array, a setting register specifying number of entry data for pre-searching, of first to N-th entry data divided and correspond respectively to the sub-blocks, and a search data changing unit changing a data arrangement order for search data input based on a value of the register. A sub-block for pre-searching searches for entry data matching with data for pre-searching in accordance with the arrangement order changed by the changing unit, in response to an instruction, and outputs a search result representing matching or non-matching. A sub-block for post-searching searches for entry data matching with data for post-searching other than the data for pre-searching, of entry data stored in association with each row of the array, based on a search result of the sub-block for pre-searching, and outputs a search result representing matching or non-matching.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: August 6, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Daigo Hayashi
  • Publication number: 20180374538
    Abstract: A semiconductor device includes an N number of sub-blocks each of including a memory cell array, a setting register specifying number of entry data for pre-searching, of first to N-th entry data divided and correspond respectively to the sub-blocks, and a search data changing unit changing a data arrangement order for search data input based on a value of the register. A sub-block for pre-searching searches for entry data matching with data for pre-searching in accordance with the arrangement order changed by the changing unit, in response to an instruction, and outputs a search result representing matching or non-matching. A sub-block for post-searching searches for entry data matching with data for post-searching other than the data for pre-searching, of entry data stored in association with each row of the array, based on a search result of the sub-block for pre-searching, and outputs a search result representing matching or non-matching.
    Type: Application
    Filed: May 1, 2018
    Publication date: December 27, 2018
    Inventor: Daigo HAYASHI