Abstract: A semiconductor memory device comprises: a plurality of first conductive layers arranged separated from each other in a first direction; a plurality of second conductive layers arranged, electrically insulated from the plurality of first conductive layers, at a different position in a second direction intersecting the first direction with respect to the first conductive layers; a plurality of memory structures; and a source structure. Respective one ends of the plurality of memory structures and one end of the source structure are electrically connected. The respective other ends of the plurality of memory structures are respectively electrically connected to different first wirings of a plurality of first wirings formed in the same layer in the first direction. The other end of the source structure is electrically connected to a second wiring formed in a different layer from the plurality of first wirings in the first direction.

Abstract: According to one embodiment, a semiconductor memory device includes: a stacked body having a stacked structure in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one by one, the stacked body including a memory region and a dummy region arranged in a first direction intersecting a stacking direction of the plurality of conductive layers, the dummy region including a first stepped portion in which at least a part of the plurality of conductive layers on an upper layer side is processed in a stepped shape and terminates at an end portion opposite to the memory region in the first direction; and first and second plate-like portions extending in the stacking direction and the first direction in the stacked body at positions in the memory region away from each other in a second direction intersecting the stacking direction and the first direction, the first and second plate-like portions being directly or indirectly connected to each other and terminating in the d

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a lower interconnect, a source line, word lines, a pillar, a pattern portion, a contact. The source line is provided in a first layer above the lower interconnect. The pattern portion is provided to be separated and insulated from the source line in the first layer. A contact is extending in a first direction, penetrating the pattern portion, and provided on the lower interconnect. A width of the contact in a second direction parallel to a surface of the substrate differs between a portion above a boundary plane that is included in the first layer and is parallel to the surface of the substrate, and a portion below the boundary plane.

Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, and a first structure that extends in a first direction orthogonal to a stacking direction of a stacked body and the stacking direction, and reaches a position deeper than an upper surface of the first conductive layer. The first structure has a first width at a bottom of the stacked body, and a second width narrower than the first width, in a first depth region from a position of the upper surface of the first conductive layer to a first depth position. A third conductive layer is connected to a side surface of the first conductive layer in the first depth region in a second direction orthogonal to the stacking direction and the first direction.

Abstract: According to one embodiment, a semiconductor storage device includes a stacked body, a columnar body, a conductive member, a plate-like portion, and a dividing portion. In the stacked body, a plurality of conductive layers and a plurality of insulating layers are alternately stacked one by one, and a stepped portion including the conductive layers is formed to be faced to an end in a first direction. The columnar body penetrates the stacked body, and includes a memory cell formed in a portion facing the conductive layer. The conductive member is electrically connected to the columnar body below the stacked body, and extends to a region laterally below the stacked body beyond the stepped portion in the first direction. The plate-like portion extends in a stacking direction of the stacked body in a lateral region of the stacked body to reach the conductive member, and extends in a second direction intersecting the first direction.

Abstract: One embodiment includes: a substrate; a memory cell array that extends in a direction vertical to the substrate and includes a memory string having a plurality of series-coupled memory cells, and a selection transistor coupled to one end of the memory string; a wiring portion that includes a plurality of first conducting layers and a plurality of interlayer insulating films, the first conducting layers functioning as gate electrodes of the memory cell and the selection transistor, the interlayer insulating film being positioned between the first conducting layers in above and below directions; and a second conducting layer arranged on end portions of the plurality of first conducting layers of the selection transistor. The first conducting layers are electrically coupled in common to the second conducting layer.

Abstract: A semiconductor storage device includes a stacked body where first layers of a first insulating material, and second layers are stacked alternately, and plate-like portions penetrating through the stacked body in a stacking direction thereof and extending in a first direction intersecting the stacking direction. Each second layer includes a first insulating area and an electrically conductive area, the former extending from a first edge portion of the stacked body in the first direction thereby occupying at least an area between a first edge portion of each plate-like portions and the first edge portion of the stacked body, and the latter being connected to the first insulating area in the first direction. A boundary between the first insulating area and the electrically conductive area is located farther from the first edge portion of plate-like portions along the first direction with respect to the first edge portion of the stacked body.

Abstract: A semiconductor memory device comprises: a plurality of first conductive layers arranged separated from each other in a first direction; a plurality of second conductive layers arranged, electrically insulated from the plurality of first conductive layers, at a different position in a second direction intersecting the first direction with respect to the first conductive layers; a plurality of memory structures; and a source structure. Respective one ends of the plurality of memory structures and one end of the source structure are electrically connected. The respective other ends of the plurality of memory structures are respectively electrically connected to different first wirings of a plurality of first wirings formed in the same layer in the first direction. The other end of the source structure is electrically connected to a second wiring formed in a different layer from the plurality of first wirings in the first direction.

Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, and a first structure that extends in a first direction orthogonal to a stacking direction of a stacked body and the stacking direction, and reaches a position deeper than an upper surface of the first conductive layer. The first structure has a first width at a bottom of the stacked body, and a second width narrower than the first width, in a first depth region from a position of the upper surface of the first conductive layer to a first depth position. A third conductive layer is connected to a side surface of the first conductive layer in the first depth region in a second direction orthogonal to the stacking direction and the first direction.

Abstract: One embodiment includes: a substrate; a memory cell array that extends in a direction vertical to the substrate and includes a memory string having a plurality of series-coupled memory cells, and a selection transistor coupled to one end of the memory string; a wiring portion that includes a plurality of first conducting layers and a plurality of interlayer insulating films, the first conducting layers functioning as gate electrodes of the memory cell and the selection transistor, the interlayer insulating film being positioned between the first conducting layers in above and below directions; and a second conducting layer arranged on end portions of the plurality of first conducting layers of the selection transistor. The first conducting layers are electrically coupled in common to the second conducting layer.

Abstract: A memory device includes a first conductive layer; a second conductive layer provided above the first conductive layer; a plurality of electrode layers stacked above the second conductive layer; a semiconductor pillar extending through the plurality of electrode layers and the second conductive layer, and connected to the first conductive layer; and a third conductive layer provided above the first conductive layer. The third conductive layer is positioned at a level substantially same as a level of the second conductive layer in an extension direction of the semiconductor pillar, and is made of a material same as a material of the second conductive layer. The third conductive layer is electrically isolated from the second conductive layer, and is electrically connected to the first conductive layer.

Abstract: A semiconductor device includes a stacked body and an insulating portion. The stacked body includes first to fourth electrode layers. The first electrode layer extends along a first direction. The second electrode layer is arranged with the first electrode layer in a second direction. The third electrode layer is provided between the first electrode layer and a word line. The fourth electrode layer is provided between the second electrode layer and the word line. The insulating portion includes first and second portions. The first portion extends along the first direction between the first electrode layer and the second electrode layer and between a portion of the third electrode layer and a portion of the fourth electrode layer. The second portion extends in the third direction between the third electrode layer and the fourth electrode layer, and through the word line.

Abstract: A memory device includes a first conductive layer; a second conductive layer provided above the first conductive layer; a plurality of electrode layers stacked above the second conductive layer; a semiconductor pillar extending through the plurality of electrode layers and the second conductive layer, and connected to the first conductive layer; and a third conductive layer provided above the first conductive layer. The third conductive layer is positioned at a level substantially same as a level of the second conductive layer in an extension direction of the semiconductor pillar, and is made of a material same as a material of the second conductive layer. The third conductive layer is electrically isolated from the second conductive layer, and is electrically connected to the first conductive layer.

Abstract: A semiconductor device includes a stacked body and an insulating portion. The stacked body includes first to fourth electrode layers. The first electrode layer extends along a first direction. The second electrode layer is arranged with the first electrode layer in a second direction. The third electrode layer is provided between the first electrode layer and a word line. The fourth electrode layer is provided between the second electrode layer and the word line. The insulating portion includes first and second portions. The first portion extends along the first direction between the first electrode layer and the second electrode layer and between a portion of the third electrode layer and a portion of the fourth electrode layer. The second portion extends in the third direction between the third electrode layer and the fourth electrode layer, and through the word line.

Abstract: According to the embodiment, the semiconductor device includes: a substrate; a stacked body; and a plurality of columnar portions. The stacked body is provided on the substrate. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The stacked body includes a stacked portion and a staircase portion. The plurality of electrode layers includes a first portion and a second portion. The columnar portions are provided in the stacked portion of the stacked body. The columnar portions extend in a stacking direction of the stacked body. The columnar portions include a semiconductor body extending in the stacking direction and a charge storage film. The second portion includes a third portion. A thickness of the third portion along the stacking direction is thinner than a thickness of the first portion along the stacking direction.

Abstract: According to the embodiment, the semiconductor device includes: a substrate; a stacked body; and a plurality of columnar portions. The stacked body is provided on the substrate. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The stacked body includes a stacked portion and a staircase portion. The plurality of electrode layers includes a first portion and a second portion. The columnar portions are provided in the stacked portion of the stacked body. The columnar portions extend in a stacking direction of the stacked body. The columnar portions include a semiconductor body extending in the stacking direction and a charge storage film. The second portion includes a third portion. A thickness of the third portion along the stacking direction is thinner than a thickness of the first portion along the stacking direction.

Abstract: An embodiment comprises: a memory cell array that includes a plurality of memory cells arranged in a stacking direction on a semiconductor substrate, and a plurality of first conductive layers arranged in the stacking direction on the semiconductor substrate and connected to the memory cells; a cover layer that covers at least some of side surfaces of each of the plurality of first conductive layers; and a second conductive layer commonly connected to ends of some of the plurality of first conductive layers. Moreover, the commonly connected ends of some of the plurality of first conductive layers and the second conductive layer are connected without being interposed by the cover layer.

Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device is disclosed. A trench is formed in a structure on a body. The structure includes first and second films alternately stacked in a first direction. A part of the first films is removed through the trench. One of the first films has a first side surface. Other one of the first films having a second side surface is positioned between the one of the first films and the body. The removing makes a distance between the trench and the second side surface shorter than a distance between the trench and the first side surface. A first space formed by the removing is filled with an insulating material. The first films are removed via a hole formed in the structure. A second space formed by the removing the first films is filled with a conductive material.

Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body including a plurality of first layers and a plurality of second layers on a substrate. The method includes forming a first slit and a second slit simultaneously by dry-etching the stacked body. The first slit causes a part of the stacked body to have a comb-shaped pattern including a plurality of line parts isolated in a first direction and extending in a second direction. The second slit surrounds the comb-shaped pattern with a closed pattern. The method includes forming a hole in the line parts of the stacked body. The method includes forming a charge storage film and a semiconductor body in the hole.

Abstract: One embodiment includes: a substrate; a memory cell array that extends in a direction vertical to the substrate and includes a memory string having a plurality of series-coupled memory cells, and a selection transistor coupled to one end of the memory string; a wiring portion that includes a plurality of first conducting layers and a plurality of interlayer insulating films, the first conducting layers functioning as gate electrodes of the memory cell and the selection transistor, the interlayer insulating film being positioned between the first conducting layers in above and below directions; and a second conducting layer arranged on end portions of the plurality of first conducting layers of the selection transistor. The first conducting layers are electrically coupled in common to the second conducting layer.