Abstract: [Problems] To eliminate flicker when a normal image is presented to user employing an optical shutter from two types or more of image under intermittent illumination of such as fluorescent lamp. [Means for Solving Problems] In a display system (10) including a display panel (11A) which can display two types or more of image sequentially and repeatedly, and an optical shutter (13) which opens with the display cycle of a specific image among the images displayed on the screen of the display panel (11A), display cycle of the specific image on the display panel (11A) is set equal to an integer multiple of the flashing cycle of intermittent illumination (15) under intermittent illumination (15) flashing periodically.

Abstract: Image processing, compressing, decompressing, transmitting, sending and receiving devices and methods, their programs and a displaying device, in which a bit plane number is increased again after the bit plane number is first reduced to enable it to largely improve or remove granular quality deterioration in a mild gradation area and a plain gradation area within an image. For data compression, a first image processor includes a block coder for executing a reversible compression of image data of pixels of a raster image and a bit plane compressor for conducting an irreversible compression of the image data. For data decompression, a second image processor includes a bit plane decompressor for carrying out an irreversible decompression of the compressed data and a block decoder for executing a reversible decoding of the compressed data, to output decompressed image data to a display for displaying a reproduced raster image. The compressed data is once stored in a memory.

Abstract: A gamma correction method including an inverse gamma correction process for inputting a value of a tone input signal Tin of X bits having non-linear tone-luminance characteristic and for outputting a tone signal Tout of Y bits (X<Y) having the tone-luminance characteristic converted to the linear characteristic, and a format conversion process for inputting the Tout and for outputting the tone output signal of (N+M) bits formed of a set of Tn and Tm which is nearest to the Tout when the Tout is expressed as A^Tn×Tm with a constant A, an index number indicated by the signal Tn of N bits and a mantissa indicated by the signal Tm of M bits.

Abstract: The present invention provides a display controller and a display apparatus capable of carrying out image display in a high-speed screen switching mode without changing a data rate of a digital transmission path while a signal itself sent through a display transmission path is kept within a standard (60 Hz). A display controller 102 sequentially outputs at least two image signals, thereby allowing an image to be displayed on a liquid crystal display section 105 in accordance with the image signals, wherein among the image signals to be outputted, an image signal of a first output image and an image signal of a second output image have a relationship that provides an image having no correlation to the first output image when image brightness values of the respective signals are added for each pixel, and wherein a frame frequency when the image signal is outputted is an integral multiple of a frame frequency for an image signal of an input image, the integral multiple being two or more.

Abstract: The invention provides: a code generation and data assignment circuit that sets the order in which a confidential image and a reversed image are displayed, based on an orthogonal code; and a shutter glass control signal generation circuit that controls so that during a period when an image signal of an image including at least part or all of the confidential image is outputted, the shutter glasses disposed between the succeeding display apparatus and the user's eyes are set in a light transmission state and during a period when another image is displayed, the shutter glasses are set in a light shielding state. The image signal of the confidential image and the image signal of the reversed image are in a relationship such that when the brightness values of the images are added together for each pixel, the resultant image has no correlation with the first output image.

Abstract: There are provided a gamma correction device enabling correct gamma correction while reducing the capacity of a lookup table, an image conversion apparatus and a display device using the same.

Abstract: An image processing apparatus, a display apparatus and an image displaying system wherein both secure and public images can be efficiently displayed with high quality without lowering the contrast of the public images. There are included a memory (101) that stores the image data of input secure and reversed images; a data assigning circuit (102) that assigns a pulse train, which has the same pulse width for the secure images and reversed images stored in the memory (101), as an image signal consisting of a pulse train to be used for displaying images on a display apparatus of PWM drive mode in which one frame is divided into a plurality of subfields to express brightness gray scales; and a shutter spectacle control signal generating circuit (103) that outputs a shutter control signal only during outputting of image signals in accordance with the secure images.

Abstract: An image processing apparatus, an image processing method, and a program thereof, and a display device are provided, in which reproduction of a secret image from one dispersed image is difficult. A secret image and a reverse image included in at least two types of images are in a relationship of forming image data of an image not correlated with the secret image when luminance values of image data respectively are added pixel by pixel.

Abstract: In an image processing/transmitting apparatus and method, graininess is suppressed while remarkably the appearance in the image area with a smooth gradation and the flat image area, the number of bit planes is reduced and then increased. The second image processing module includes a bit adding module executing bit adding based on the two-dimensional dither matrix for compressed data read from memory and obtaining decompressed data, an LPF processing threshold value generator obtaining a threshold value from decompressed data, and an LPF processing module attaining a difference between decompressed data of a pixel and decompressed data of a peripheral pixel, which sets a result of weighted mean processing for decompressed data of the pertinent and peripheral pixels to the output image data if the difference is within the threshold, and which sets the decompressed data of an arbitrary pixel to the output image data if the difference value>threshold.

Abstract: An image processing device includes a detector for detecting a linear-interpolation-applicable area and an expansion corrector for performing a gradation expanding process on the linear-interpolation-applicable area detected by the detector. When a detector 11 detects a linear-interpolation-applicable area, if the gradation values of pixels preceding and following a pixel where a gradation change in a predetermined range is detected are the same as each other, then the detector judges the gradation change as being caused by a noise or the like, and regards the gradation value of the pixel where the gradation change is detected as the gradation values of pixels preceding and following the pixel.

Abstract: By sequentially scanning pixel lines of an image signal that has been received as input linear interpolation application regions, which are regions in which gray-level changes are to be smoothed, are detected for each line of the input signal, and the detected linear interpolation application regions are then subjected to an gray-level extension process. The regions that have been subjected to the gray-level extension process are further subjected to a process of limiting, to within prescribed values, gray-level changes in a second direction that differs from the direction in which the linear interpolation application region detection process was carried out.

Abstract: A level shift circuit operates normally when amplitude of input signal is small and amplitude of output signal is large. First and second terminals receive an input signal and its complementary signal having a first amplitude. Third and fourth terminals output an output signal and its complementary signal having a second amplitude, which is larger than the first amplitude. Output circuit comprises first and second transistors of first polarity respectively connected between first power supply and fourth and third terminals, respectively. Third and fourth transistors of second polarity, respectively, are connected between second power supply and fourth and third terminals, respectively, having control ends connected to the third and the fourth terminals, respectively. First current control circuit controls so that a current driving the fourth terminal flows through the first transistor according to the input signal and the complementary signal of the output signal.

Abstract: To realize an area reduction of a semiconductor chip without adding a process, and to provide a semiconductor chip structure having an excellent pressure balance when mounted. In the structure of a semiconductor chip in which control/power supply lines are formed on a glass substrate, connecting terminals for electrically connecting with the control/power supply lines are provided in alignment in the longitudinal direction of the semiconductor device, whereby the wiring length within the semiconductor chip can be suppressed to be minimum. Since the wiring length is shortened, the width of the wirings within the semiconductor chip is narrowed, so that the area of the semiconductor chip is reduced.

Abstract: A level shift circuit operates normally when amplitude of input signal is small and amplitude of output signal is large. First and second terminals receive an input signal and its complementary signal having a first amplitude. Third and fourth terminals output an output signal and its complementary signal having a second amplitude, which is larger than the first amplitude. Output circuit comprises first and second transistors of first polarity respectively connected between first power supply and fourth and third terminals, respectively. Third and fourth transistors of second polarity, respectively, are connected between second power supply and fourth and third terminals, respectively, having control ends connected to the third and the fourth terminals, respectively. First current control circuit controls so that a current driving the fourth terminal flows through the first transistor according to the input signal and the complementary signal of the output signal.

Abstract: Image processing, compressing, decompressing, transmitting, sending and receiving devices and methods, their programs and a displaying device, in which a bit plane number is increased again after the bit plane number is first reduced to enable it to largely improve or remove granular quality deterioration in a mild gradation area and a plain gradation area within an image. For data compression, a first image processor includes a block coder for executing a reversible compression of image data of pixels of a raster image and a bit plane compressor for conducting an irreversible compression of the image data. For data decompression, a second image processor includes a bit plane decompressor for carrying out an irreversible decompression of the compressed data and a block decoder for executing a reversible decoding of the compressed data, to output decompressed image data to a display for displaying a reproduced raster image. The compressed data is once stored in a memory.

Abstract: There are provided a gamma correction device enabling correct gamma correction while reducing the capacity of a lookup table, an image conversion apparatus and a display device using the same.

Abstract: A gamma correction method including an inverse gamma correction process for inputting a value of a tone input signal Tin of X bits having non-linear tone-luminance characteristic and for outputting a tone signal Tout of Y bits (X<Y) having the tone-luminance characteristic converted to the linear characteristic, and a format conversion process for inputting the Tout and for outputting the tone output signal of (N+M) bits formed of a set of Tn and Tm which is nearest to the Tout when the Tout is expressed as AˆTn×Tm with a constant A, an index number indicated by the signal Tn of N bits and a mantissa indicated by the signal Tm of M bits.

Abstract: An image processing apparatus, an image transmission apparatus, a display, an image processing method and an image transmission method, capable of suppressing tone or gray-level distortion before and after dithering as well as reducing and then increasing the number of bit-planes of an image. An image processing apparatus comprises a first image processor for performing multi-level dithering based on a two-dimensional dither matrix to reduce the bit-plane number of a raster image as an original image, a memory for storing image data of the raster image whose bit-plane number has been reduced by the first image processor, and a second image processor for performing bit addition for the image data read out from the memory to increase the bit-plane number thereof.

Abstract: The present invention provides an image processing method of a hold type display device, a driving method of the display device and a display device driven by the method, for improving the moving picture quality without lowering the luminance and the contrast. In the image processing method for dividing one frame into sub frames, luminance components of a certain sub frame are distributed to other sub frames, so as to generate sub frame with luminance components higher than the average in the one frame and sub frame with luminance components lower than the average in the one frame, as a result of which the amount of luminance during one frame period is kept constant before and after the distribution of luminance components.

Abstract: To realize an area reduction of a semiconductor chip without adding a process, and to provide a semiconductor chip structure having an excellent pressure balance when mounted. In the structure of a semiconductor chip in which control/power supply lines are formed on a glass substrate, connecting terminals for electrically connecting with the control/power supply lines are provided in alignment in the longitudinal direction of the semiconductor device, whereby the wiring length within the semiconductor chip can be suppressed to be minimum. Since the wiring length is shortened, the width of the wirings within the semiconductor chip is narrowed, so that the area of the semiconductor chip is reduced.