Abstract: A TFC selection apparatus includes: a SIR calculation unit calculating SIR by using a CPICH symbol of receive data; a conversion unit obtaining STFC(m) which contains m pieces of TFC corresponding to the calculated SIR; a total transmit power calculation unit selecting TFC corresponding to the obtained STFC(m) from a TFCS which is a set of TFCs sequenced in proportion to a magnitude of total transmit power, and calculating total transmit power of TFC included in the TFCS in order indicated by a search direction signal, beginning with the selected TFC as a starting point; and a TFC selection unit generating the search direction signal based on the calculated total transmit power of the TFC as the starting point, and selecting an optimum TFC to be applied to transmit data from the TFCS, wherein the TFC selection unit selects TFC as the optimum TFC corresponding to total transmit power which indicates less than or equal to as well as approximate to a maximum value allowed for the transmit data.

Abstract: A signal receiving apparatus which can reduce a circuit scale to reduce a cost in a mobile wireless communication system which transmits and receives a spread spectrum signal is provided. The signal receiving apparatus includes a filter coefficient updating unit 104 which generates a filter coefficient w on the basis of an input signal x, a transformational despreading unit 101 which performs a despreading process to the input signal x, and an FIR filter 103 which performs multiplication by using a despreading output z output from the transformational despreading unit and the filter coefficient w output from the filter coefficient updating unit 104 as inputs to output a result which the multiplication results are added as a signal data symbol output S. The transformational despreading unit 101 obtains a despreading output by addition and subtraction between the input signal x and a spread code sequence c.

Abstract: A TFC selection apparatus includes: a SIR calculation unit calculating SIR by using a CPICH symbol of receive data; a conversion unit obtaining STFC(m) which contains m pieces of TFC corresponding to the calculated SIR; a total transmit power calculation unit selecting TFC corresponding to the obtained STFC(m) from a TFCS which is a set of TFCs sequenced in proportion to a magnitude of total transmit power, and calculating total transmit power of TFC included in the TFCS in order indicated by a search direction signal, beginning with the selected TFC as a starting point; and a TFC selection unit generating the search direction signal based on the calculated total transmit power of the TFC as the starting point, and selecting an optimum TFC to be applied to transmit data from the TFCS, wherein the TFC selection unit selects TFC as the optimum TFC corresponding to total transmit power which indicates less than or equal to as well as approximate to a maximum value allowed for the transmit data.

Abstract: A signal receiving apparatus which can reduce a circuit scale to reduce a cost in a mobile wireless communication system which transmits and receives a spread spectrum signal is provided. The signal receiving apparatus includes a filter coefficient updating unit 104 which generates a filter coefficient w on the basis of an input signal x, a transformational despreading unit 101 which performs a despreading process to the input signal x, and an FIR filter 103 which performs multiplication by using a despreading output z output from the transformational despreading unit and the filter coefficient w output from the filter coefficient updating unit 104 as inputs to output a result which the multiplication results are added as a signal data symbol output S. The transformational despreading unit 101 obtains a despreading output by addition and subtraction between the input signal x and a spread code sequence c.

Abstract: A data processing apparatus capable of preventing contention of memory access between the HARQ synthesis and rate dematching in the HARQ processing using two or more single-port memories is provided. A buffer includes two physical memories. One of the physical memories is used as an even address memory, and the other is used as an odd address memory. With respect to access to the buffer conducted by the HARQ synthesis and rate dematching, access control is conducted so as to make the rate dematching access the odd address memory when the HARQ synthesis accesses the even address memory.

Abstract: (3n+1)th (n=0, 1, 2, . . . , M/3?1) input data is stored in a first memory 102, (3n+2)th (n=0, 1, 2, . . . , M/3?1) input data is stored in a second memory 103, and (3n+3)th (n=0, 1, 2, . . . , M/3?1) input data is stored in a third memory 104. Information bit, first parity bit, and second parity bit that have been read out by 3 bits are held in an information bit queue 108, a first parity bit queue 109, and a second parity bit queue 110, respectively, to control data supply to the rate dematching circuits 111 and 112 by these queues 108, 109 and 110.

Abstract: A parallel computation processor being capable of high-speed loop operation. When instruction decoders decode the VLOOP instruction, which triggers loop operation, an instruction buffer starts storing normal instructions. The instruction buffer dispatches a VLIW instruction composed of n pieces of normal instructions to execution units each time n pieces of instructions are stored therein. The execution units concurrently execute the instructions. After all instructions comprised in a loop have been stored in the buffer and once dispatched as VLIW instructions to be executed, the loop is executed repeatedly.

Abstract: A data processing apparatus capable of preventing contention of memory access between the HARQ synthesis and rate dematching in the HARQ processing using two or more single-port memories is provided. A buffer includes two physical memories. One of the physical memories is used as an even address memory, and the other is used as an odd address memory. With respect to access to the buffer conducted by the HARQ synthesis and rate dematching, access control is conducted so as to make the rate dematching access the odd address memory when the HARQ synthesis accesses the even address memory.

Abstract: An address generating circuit, in which address generation by a modulo addition is executed at high speed, is provided. The address generating circuit makes, a two input adder that adds an address and a renewing step, a three input adder and subtracter that adds the address and the renewing step and further adds the size of a modulo area to this added result or subtracts the size of the modulo area from this added result, and a selection judging circuit that generates a selection signal for selecting one of the outputs from the two input adder and the three input adder and subtracter, work in parallel and independently. And a multiplexer selects one of the outputted results from the two input adder and the three input adder and subtracter based on the selection signal from the selection judging circuit.

Abstract: (3n+1)th (n=0, 1, 2, . . . , M/3−1) input data is stored in a first memory 102, (3n+2)th (n=0, 1, 2, . . . , M/3−1) input data is stored in a second memory 103, and (3n+3)th (n=0, 1, 2, . . . , M/3−1) input data is stored in a third memory 104. Information bit, first parity bit, and second parity bit that have been read out by 3 bits are held in an information bit queue 108, a first parity bit queue 109, and a second parity bit queue 110, respectively, to control data supply to the rate dematching circuits 111 and 112 by these queues 108, 109 and 110.

Abstract: A rake reception apparatus which receives and rake-combines spread signals on a path basis includes finger receivers, a switch, an adder, and a buffer. The finger receivers de-spread reception signals on a path basis. The switch sequentially selects de-spread data one by one on a path basis which are output from the plurality of finger receivers. The adder adds the data selected by the switch to a rake combining interim result corresponding to the data and outputs the result as a rake combining interim result after updating. The buffer holds the rake combining interim result output from the adder and outputs a rake combining interim result corresponding to data selected by the switch to the adder. A rake reception method is also disclosed.

Abstract: A signal decoding system performs variable length decoding and inverse quantization at high speed. From bit stream temporarily held in a bit string buffer, a bit string is parsed as a table address to look up a lookup table in a table looking-up unit and a table selecting unit. By looking up the table, variable length decoding is performed simultaneously for maximum two codewords. Furthermore, the decoded data is inversely quantized in parallel by using inverse quantizars. The results of inverse quantization are stored at appropriate positions in the block by the block storage unit.

Abstract: A parallel computation processor being capable of high-speed loop operation. When instruction decoders decode the VLOOP instruction, which triggers loop operation, an instruction buffer starts storing normal instructions. The instruction buffer dispatches a VLIW instruction composed of n pieces of normal instructions to execution units each time n pieces of instructions are stored therein. The execution units concurrently execute the instructions. After all instructions comprised in a loop have been stored in the buffer and once dispatched as VLIW instructions to be executed, the loop is executed repeatedly.

Abstract: A signal decoding system performs variable length decoding and inverse quantization at high speed. From a bit stream temporarily held in a bit string buffer, the bit string is parsed as a table address for a lookup table in a table looking-up unit and a table selecting unit. By looking up the table address in the lookup table, variable length decoding is performed simultaneously for a maximum of two codewords. Furthermore, the decoded data is inversely quantized in parallel by using inverse quantizers. The results of inverse quantization are stored at appropriate positions in the block by the block storage unit.

Abstract: An address generating circuit, in which address generation by a modulo addition is executed at high speed, is provided. The address generating circuit makes, a two input adder that adds an address and a renewing step, a three input adder and subtracter that adds the address and the renewing step and further adds the size of a modulo area to this added result or subtracts the size of the modulo area from this added result, and a selection judging circuit that generates a selection signal for selecting one of the outputs from the two input adder and the three input adder and subtracter, work in parallel and independently. And a multiplexer selects one of the outputted results from the two input adder and the three input adder and subtracter based on the selection signal from the selection judging circuit.

Abstract: Multipliers 107 through 110 carry out an multiplication operation with two data out of the four data transferred from a memory over buses 101 through 104. The multiplication results are subjected to an addition or subtraction operation with each other in adder-subtracters 111 and 112. The operation results obtained by the adder-subtracters 111 and 112 are supplied to adders 113 and 114 where they are added to values held by accumulators 115 and 116. A latch circuit 105 supplies the data transferred through the bus 102 to the multiplier 109 when a control signal 106 indicates “ON”. The latch circuit 105 temporarily holds the data transferred through the bus 102 and supplies the data held therein to the multiplier 109 when a control signal 106 indicates “OFF”.