Patents by Inventor Daijiro Inami

Daijiro Inami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5812030
    Abstract: An amplifier section is supplied with an electric signal outputted from a light-sensitive detector. The amplifier section comprises an amplifying circuit for amplifying the electric signal into an amplified signal having an amplified level. A producing section produces a control signal on the basis of the amplified signal and a reference voltage. A resistor section is connected to the amplifying circuit in parallel. The resistor section has a variable resistance which is varied in accordance with the control signal. A capacitor section has a capacitor and connects the input of the amplifying circuit and the output of the amplifying circuit through the capacitor in response to the control signal.
    Type: Grant
    Filed: June 20, 1996
    Date of Patent: September 22, 1998
    Assignee: NEC Corporation
    Inventors: Daijiro Inami, Yasuhiro Otsuka
  • Patent number: 5612810
    Abstract: An optical receiving apparatus of the present invention comprises an opto-electric conversion element for converting an optical signal into an electric signal, a differential type preamplifier for sending a non-inverting phase signal and a inverting phase signal of the electric signal and a first and second peak hold circuits for holding peak values of the respective non-inverting and inverting phase signals. Further, the optical receiving apparatus of the present invention comprises a first adder for adding the inverting phase signal to the non-inverting phase peak signal from the first peak hold circuit and a second adder for adding the non-inverting phase signal to the inverting phase peak signal from the second peak hold circuit.
    Type: Grant
    Filed: September 12, 1995
    Date of Patent: March 18, 1997
    Assignee: NEC Corporation
    Inventors: Daijiro Inami, Yuichi Sato
  • Patent number: 5587667
    Abstract: An output buffer circuit is provided, which enables to reduce the delay of a digital output signal with respect to an input digital signal. The output buffer circuit includes first and second FETs serially connected to each other. A gate of the first FET is applied with a first digital input signal. A gate of the second FET is applied with a second digital input signal. The first and second FETs operate to be opposite or complementary in logic state to each other. A digital output signal is taken out from a connection point of the first and second FETs. The circuit further includes a current source for causing a bias current having the same direction or polarity as that of a drain current of the first FET to flow through the first FET in the pseudo-OFF state. A turn-on speed of the first FET from the pseudo-OFF state to the ON state is enhanced by the bias current.
    Type: Grant
    Filed: December 19, 1995
    Date of Patent: December 24, 1996
    Assignee: NEC Corporation
    Inventors: Daijiro Inami, Yuichi Sato
  • Patent number: 5243346
    Abstract: In a digital-to-analog converting device for converting an input digital signal into an output analog signal, a converting circuit converts the input digital signal into a first and a second digital signal which are alternatingly produced in parallel in response to clock pulses. A first and a second decoder are for decoding the first and the second digital signals into a first and a second decoded parallel digital signal. A first and a second parallel-serial converter are for converting the first and the second decoded parallel digital signals into a first and a second serial digital signal in response to an oversampling clock pulses. A first and a second digital-to-analog converter are for converting the first and the second serial digital signals into a first and a second analog signal. An analog adder adds the first and the second analog signals into a sum analog signal. An analog integrator is for integrating the sum analog signal into the output analog signal.
    Type: Grant
    Filed: December 19, 1991
    Date of Patent: September 7, 1993
    Assignee: NEC Corporation
    Inventor: Daijiro Inami