Patents by Inventor Daijiro Otani
Daijiro Otani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10425052Abstract: In some embodiments, a differential input stage comprises a first n-type metal oxide semiconductor transistor (NMOS) pair coupled to a first input and a second input, a second NMOS pair coupled to the first input, a first output node, the second input, and a second output node, a first diode coupled to the first NMOS pair and the first output node, a second diode coupled to the first NMOS pair and the second output node, and a cascaded current source coupled to the first NMOS pair and the second NMOS pair.Type: GrantFiled: November 7, 2017Date of Patent: September 24, 2019Assignee: Texas Instruments IncorporatedInventor: Daijiro Otani
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Publication number: 20190140607Abstract: In some embodiments, a differential input stage comprises a first n-type metal oxide semiconductor transistor (NMOS) pair coupled to a first input and a second input, a second NMOS pair coupled to the first input, a first output node, the second input, and a second output node, a first diode coupled to the first NMOS pair and the first output node, a second diode coupled to the first NMOS pair and the second output node, and a cascaded current source coupled to the first NMOS pair and the second NMOS pair.Type: ApplicationFiled: November 7, 2017Publication date: May 9, 2019Inventor: Daijiro OTANI
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Patent number: 9973152Abstract: One example includes an amplifier system. The system includes a gain stage configured to conduct a gain current in response to an input voltage. The system also includes a current limit stage coupled to the gain stage and being configured to one of source and sink the gain current and to define a limit amplitude of the gain current during a current limit condition. The system further includes an output stage coupled to the gain stage and configured to conduct an output current through an output node in response to the gain current, the output current having a maximum amplitude during the current limit condition that is proportional to the limit amplitude.Type: GrantFiled: November 14, 2016Date of Patent: May 15, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Daijiro Otani, Keita Ikai
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Patent number: 9641066Abstract: A current driver is coupled to an inductor; a digital control for regulation of the current driver turns the current driver on or off coupled to the current driver; a comparator output coupled to the input of the digital control for regulation of the driver with inputs to compare a voltage of the inductor to a target voltage, a digital control for selection of one of a set of peaks and valleys of allowable current levels of the current driver, the digital control for selection of one of a set of peaks and valleys coupled to the output of the comparator and an input of the current driver, the digital control for the peak/valley current to monitor the duration of each high and low output state of the comparator output to determine the selection of one of the set of peak and valley of allowable current levels for the current driver.Type: GrantFiled: July 30, 2013Date of Patent: May 2, 2017Assignee: Texas Instruments IncorporatedInventors: Naoyuki Tsuruoka, Daijiro Otani, Keita Ikai, Masaki Yamashita
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Publication number: 20170063313Abstract: One example includes an amplifier system. The system includes a gain stage configured to conduct a gain current in response to an input voltage. The system also includes a current limit stage coupled to the gain stage and being configured to one of source and sink the gain current and to define a limit amplitude of the gain current during a current limit condition. The system further includes an output stage coupled to the gain stage and configured to conduct an output current through an output node in response to the gain current, the output current having a maximum amplitude during the current limit condition that is proportional to the limit amplitude.Type: ApplicationFiled: November 14, 2016Publication date: March 2, 2017Inventors: Daijiro Otani, Keita Ikai
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Patent number: 9495982Abstract: One example includes an amplifier system. The system includes a gain stage configured to conduct a gain current in response to an input voltage. The system also includes a current limit stage coupled to the gain stage and being configured to one of source and sink the gain current and to define a limit amplitude of the gain current during a current limit condition. The system further includes an output stage coupled to the gain stage and configured to conduct an output current through an output node in response to the gain current, the output current having a maximum amplitude during the current limit condition that is proportional to the limit amplitude.Type: GrantFiled: May 1, 2014Date of Patent: November 15, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Daijiro Otani, Keita Ikai
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Publication number: 20150318831Abstract: One example includes an amplifier system. The system includes a gain stage configured to conduct a gain current in response to an input voltage. The system also includes a current limit stage coupled to the gain stage and being configured to one of source and sink the gain current and to define a limit amplitude of the gain current during a current limit condition. The system further includes an output stage coupled to the gain stage and configured to conduct an output current through an output node in response to the gain current, the output current having a maximum amplitude during the current limit condition that is proportional to the limit amplitude.Type: ApplicationFiled: May 1, 2014Publication date: November 5, 2015Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: DAIJIRO OTANI, KEITA IKAI
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Patent number: 8963472Abstract: An apparatus, comprises three driver FETs coupled at their sources; note-driver circuit; a first sense FET coupled to the sources of the three driver FETs; a current mirror having the first sense FET and a mirror FET; wherein the first sense FET is coupled to the mirror FET; a first transconductance amplifier coupled to the first sense FET; a second amplifier coupled to the current mirror, and an output of the first transconductance amplifier is an input to the second amplifier.Type: GrantFiled: March 20, 2013Date of Patent: February 24, 2015Assignee: Texas Instruments IncorporatedInventors: Daijiro Otani, Nakoyuki Tsuruoka, Masaki Yamashita
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Patent number: 8737012Abstract: An apparatus for use with a hard disk drive, comprising: a selectable notch filter with a selectable notch frequency; a shock sensor of the hard disk drive, coupled to the selectable notch filter, the shock sensor having at least one resonance frequency; a flip flop coupled to an output of the notch filter and an output of the shock sensor; a calibration logic coupled to an output of the flip flop, wherein an output of the calibration logic is coupled to a selection input of the selectable notch filter.Type: GrantFiled: September 11, 2012Date of Patent: May 27, 2014Assignee: Texas Instruments IncorporatedInventor: Daijiro Otani
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Publication number: 20140063652Abstract: An apparatus for use with a hard disk drive, comprising: a selectable notch filter with a selectable notch frequency; a shock sensor of the hard disk drive, coupled to the selectable notch filter, the shock sensor having at least one resonance frequency; a flip flop coupled to an output of the notch filter and an output of the shock sensor; a calibration logic coupled to an output of the flip flop, wherein an output of the calibration logic is coupled to a selection input of the selectable notch filter.Type: ApplicationFiled: September 11, 2012Publication date: March 6, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Daijiro Otani
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Publication number: 20140055107Abstract: A current driver is coupled to an inductor; a digital control for regulation of the current driver turns the current driver on or off coupled to the current driver; a comparator output coupled to the input of the digital control for regulation of the driver with inputs to compare a voltage of the inductor to a target voltage, a digital control for selection of one of a set of peaks and valleys of allowable current levels of the current driver, the digital control for selection of one of a set of peaks and valleys coupled to the output of the comparator and an input of the current driver, the digital control for the peak/valley current to monitor the duration of each high and low output state of the comparator output to determine the selection of one of the set of peak and valley of allowable current levels for the current driver.Type: ApplicationFiled: July 30, 2013Publication date: February 27, 2014Inventors: Naoyuki Tsuruoka, Daijiro Otani, Keita Ikai, Masaki Yamashita
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Publication number: 20130278199Abstract: An apparatus, comprises three driver FETs coupled at their sources; note-driver circuit; a first sense FET coupled to the sources of the three driver FETs; a current mirror having the first sense FET and a mirror FET; wherein the first sense FET is coupled to the mirror FET; a first transconductance amplifier coupled to the first sense FET; a second amplifier coupled to the current mirror, and an output of the first transconductance amplifier is an input to the second amplifier.Type: ApplicationFiled: March 20, 2013Publication date: October 24, 2013Inventors: Daijiro Otani, Nakoyuki Tsuruoka, Masaki Yamashita
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Patent number: 7835096Abstract: One embodiment of the invention includes a disk-drive write head fault detection system. The system includes an output stage configured to generate a monitored current through the disk-drive write head. The system also includes an open-circuit fault detector configured to compare a magnitude of a first reference current with a magnitude of the monitored current to detect an open-circuit fault condition associated with the disk-drive write head. The system further includes a short-to-ground fault detector configured to compare a magnitude of a second reference current with the magnitude of the monitored current to detect a short-to-ground fault condition associated with the disk-drive write head.Type: GrantFiled: November 10, 2008Date of Patent: November 16, 2010Assignee: Texas Instuments IncorporatedInventor: Daijiro Otani
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Publication number: 20100122118Abstract: One embodiment of the invention includes a disk-drive write head fault detection system. The system includes an output stage configured to generate a monitored current through the disk-drive write head. The system also includes an open-circuit fault detector configured to compare a magnitude of a first reference current with a magnitude of the monitored current to detect an open-circuit fault condition associated with the disk-drive write head. The system further includes a short-to-ground fault detector configured to compare a magnitude of a second reference current with the magnitude of the monitored current to detect a short-to-ground fault condition associated with the disk-drive write head.Type: ApplicationFiled: November 10, 2008Publication date: May 13, 2010Inventor: Daijiro Otani