Patents by Inventor Daiki FUKUNAGA

Daiki FUKUNAGA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12142440
    Abstract: A multilayer ceramic capacitor includes a laminated body and first and second external electrodes respectively on both end surfaces of the laminated body. When regions where first internal electrodes or second internal electrodes are not present are regarded as side margin portions in a cross section of the laminated body as viewed from the laminating direction, the side margin portions include multiple side margin layers, and the content of Si in the side margin layer closest to the internal electrode is lower than that in the side margin layer other than the side margin layer closest to the internal electrode.
    Type: Grant
    Filed: September 20, 2023
    Date of Patent: November 12, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hideaki Tanaka, Daiki Fukunaga, Koji Moriyama
  • Publication number: 20240343496
    Abstract: A control system controls a conveyance system including a transfer robot capable of autonomously moving and capable of conveying an article to be conveyed. The control system acquires conveyance destination information from a wagon capable of accommodating the article. The conveyance destination information indicates a destination of conveyance of the article. The control system causes the transfer robot to autonomously move such that the transfer robot conveys the wagon to the destination of conveyance indicated by the acquired conveyance destination information.
    Type: Application
    Filed: February 27, 2024
    Publication date: October 17, 2024
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Daiki FUKUNAGA, Shiro ODA, Takeshi MATSUI
  • Publication number: 20240342893
    Abstract: A robot system includes a mobile robot. The mobile robot includes a power receiving pad and a sensor. The power receiving pad is configured to receive power supply from a power transmission pad of a charger. The sensor is disposed at a position displaced from the power receiving pad in an up-down direction, and configured to detect a surrounding object. The power receiving pad is provided as inclined in the up-down direction so as to project toward the sensor. The power transmission pad is provided as inclined in the up-down direction so as to face the power receiving pad. A distal end of the sensor on a side toward the power transmission pad is disposed on an outer side, in top view, with respect to the distal end of the power receiving pad.
    Type: Application
    Filed: March 4, 2024
    Publication date: October 17, 2024
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Daiki FUKUNAGA, Shiro ODA, Takeshi MATSUI
  • Publication number: 20240345590
    Abstract: A transport system according to the present disclosure includes a mobile robot that moves with a wagon mounted thereon, the wagon having a plurality of convex portions that protrude downward. The mobile robot includes a platform that has a mounting surface on which the wagon is placed and that enters under the wagon, a raising and lowering mechanism that raises and lowers the platform to deliver the wagon, a plurality of concave portions provided corresponding to the plurality of convex portions of the wagon, an optical sensor provided on a side surface of at least one concave portion among the plurality of concave portions, and a detection unit that detects that at least one of the plurality of convex portions is inserted into the at least one concave portion according to a detection result of the optical sensor.
    Type: Application
    Filed: March 29, 2024
    Publication date: October 17, 2024
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Daiki FUKUNAGA, Shiro ODA, Takeshi MATSUI
  • Publication number: 20240312712
    Abstract: An electronic component includes a laminate in which a plurality of dielectric layers and a plurality of internal electrodes are alternately laminated and external electrodes electrically connected to the internal electrodes. A side margin portion as a region in which the plurality of internal electrodes is not provided when a section of the laminate having the length direction and the width direction is viewed from the laminating direction includes a plurality of side margin layers laminated in the width direction. An outer layer portion as a region in which the plurality of internal electrodes is not provided except for the side margin portion when a section of the laminate including the laminating direction and the width direction is viewed from the length direction includes a plurality of layer-margin layers laminated in the laminating direction.
    Type: Application
    Filed: May 28, 2024
    Publication date: September 19, 2024
    Inventors: Daiki FUKUNAGA, Hideaki TANAKA, Masahiro WAKASHIMA, Daisuke HAMADA, Hironori TSUTSUMI, Satoshi MAENO, Ryota ASO, Koji MORIYAMA, Akihiro TSURU
  • Patent number: 12020867
    Abstract: An electronic component includes a laminate in which a plurality of dielectric layers and a plurality of internal electrodes are alternately laminated and external electrodes electrically connected to the internal electrodes. A side margin portion as a region in which the plurality of internal electrodes is not provided when a section of the laminate having the length direction and the width direction is viewed from the laminating direction includes a plurality of side margin layers laminated in the width direction. An outer layer portion as a region in which the plurality of internal electrodes is not provided except for the side margin portion when a section of the laminate including the laminating direction and the width direction is viewed from the length direction includes a plurality of layer-margin layers laminated in the laminating direction.
    Type: Grant
    Filed: February 16, 2023
    Date of Patent: June 25, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Daiki Fukunaga, Hideaki Tanaka, Masahiro Wakashima, Daisuke Hamada, Hironori Tsutsumi, Satoshi Maeno, Ryota Aso, Koji Moriyama, Akihiro Tsuru
  • Publication number: 20240087814
    Abstract: A multilayer ceramic capacitor includes a second alloy portion including one metal element provided in a greatest amount among metal elements of an internal electrode layer, and one or more metal elements among a metal group including Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, and Y is provided between a second dielectric ceramic layer and a first internal electrode layer, and between a second dielectric ceramic layer and a second internal electrode layer, respectively.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 14, 2024
    Inventors: Yuta KUROSU, Yuta SAITO, Masahiro WAKASHIMA, Daiki FUKUNAGA, Yu TSUTSUI
  • Patent number: 11875949
    Abstract: A method of manufacturing an electronic component includes preparing an unfired multilayer body including first and second main surfaces facing each other in a stacking direction, first and second side surfaces facing each other in a width direction, and first and second end surfaces facing each other in a length direction, bonding one main surface of the unfired multilayer body to an elongated first adhesive sheet, conveying the first adhesive sheet in a first direction in which the first adhesive sheet approaches an elongated second adhesive sheet, and bonding one side surface of the unfired multilayer body to the second adhesive sheet, conveying the second adhesive sheet in a second direction different from the first direction to peel off the unfired multilayer body from the first adhesive sheet, polishing another side surface of the unfired multilayer body, and forming a first insulating layer on the polished another side surface.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: January 16, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Daiki Fukunaga
  • Publication number: 20240013982
    Abstract: A multilayer ceramic capacitor includes a laminated body and first and second external electrodes respectively on both end surfaces of the laminated body. When regions where first internal electrodes or second internal electrodes are not present are regarded as side margin portions in a cross section of the laminated body as viewed from the laminating direction, the side margin portions include multiple side margin layers, and the content of Si in the side margin layer closest to the internal electrode is lower than that in the side margin layer other than the side margin layer closest to the internal electrode.
    Type: Application
    Filed: September 20, 2023
    Publication date: January 11, 2024
    Inventors: Hideaki TANAKA, Daiki FUKUNAGA, Koji MORIYAMA
  • Patent number: 11869724
    Abstract: A multilayer ceramic capacitor includes a second alloy portion including one metal element provided in a greatest amount among metal elements of an internal electrode layer, and one or more metal elements among a metal group including Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, and Y is provided between a second dielectric ceramic layer and a first internal electrode layer, and between a second dielectric ceramic layer and a second internal electrode layer, respectively.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: January 9, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yuta Kurosu, Yuta Saito, Masahiro Wakashima, Daiki Fukunaga, Yu Tsutsui
  • Patent number: 11798746
    Abstract: A multilayer ceramic capacitor includes a laminated body and first and second external electrodes respectively on both end surfaces of the laminated body. When regions where first internal electrodes or second internal electrodes are not present are regarded as side margin portions in a cross section of the laminated body as viewed from the laminating direction, the side margin portions include multiple side margin layers, and the content of Si in the side margin layer closest to the internal electrode is lower than that in the side margin layer other than the side margin layer closest to the internal electrode.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: October 24, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hideaki Tanaka, Daiki Fukunaga, Koji Moriyama
  • Patent number: 11721490
    Abstract: A method of manufacturing a multilayer ceramic capacitor includes printing an internal electrode pattern on a dielectric layer, forming a dielectric pattern in a region other than a region in which the internal electrode pattern is printed, laminating dielectric layers to form a multilayer body, exposing the internal electrode pattern and the dielectric pattern from a side surface of the multilayer body, removing at least a portion of the exposed dielectric pattern, and forming a dielectric gap layer on the side surface.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: August 8, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yu Tsutsui, Yuta Kurosu, Daiki Fukunaga, Yuta Saito, Masahiro Wakashima
  • Publication number: 20230202814
    Abstract: A transport robot is configured to transfer a transported article to and from an installed shelf by passing the installed shelf. A shelf portion that holds the transported article is configured to pass the installed shelf by the transport robot traveling. A chassis is configured to support the shelf portion. A stand is disposed on a first end portion side in a right-left direction of the transport robot, and extends upward from the chassis. An operating unit is configured to be installed on the stand.
    Type: Application
    Filed: November 10, 2022
    Publication date: June 29, 2023
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Satoshi TOYOSHIMA, Daiki FUKUNAGA, Shiro ODA, Nobuyuki TOMATSU, Keisuke FUKUNAGA, Zixun MEI, Takeshi MATSUI, Toshiyuki KAWABE
  • Publication number: 20230197340
    Abstract: An electronic component includes a laminate in which a plurality of dielectric layers and a plurality of internal electrodes are alternately laminated and external electrodes electrically connected to the internal electrodes. A side margin portion as a region in which the plurality of internal electrodes is not provided when a section of the laminate having the length direction and the width direction is viewed from the laminating direction includes a plurality of side margin layers laminated in the width direction. An outer layer portion as a region in which the plurality of internal electrodes is not provided except for the side margin portion when a section of the laminate including the laminating direction and the width direction is viewed from the length direction includes a plurality of layer-margin layers laminated in the laminating direction.
    Type: Application
    Filed: February 16, 2023
    Publication date: June 22, 2023
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Daiki FUKUNAGA, Hideaki TANAKA, Masahiro WAKASHIMA, Daisuke HAMADA, Hironori TSUTSUMI, Satoshi MAENO, Ryota ASO, Koji MORIYAMA, Akihiro TSURU
  • Publication number: 20230178305
    Abstract: A multilayer ceramic capacitor includes a second alloy portion including one metal element provided in a greatest amount among metal elements of an internal electrode layer, and one or more metal elements among a metal group including Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, and Y is provided between a second dielectric ceramic layer and a first internal electrode layer, and between a second dielectric ceramic layer and a second internal electrode layer, respectively.
    Type: Application
    Filed: January 30, 2023
    Publication date: June 8, 2023
    Inventors: Yuta KUROSU, Yuta SAITO, Masahiro WAKASHIMA, Daiki FUKUNAGA, Yu TSUTSUI
  • Patent number: 11610736
    Abstract: An electronic component includes a laminate in which a plurality of dielectric layers and a plurality of internal electrodes are alternately laminated and external electrodes electrically connected to the internal electrodes. A side margin portion as a region in which the plurality of internal electrodes is not provided when a section of the laminate having the length direction and the width direction is viewed from the laminating direction includes a plurality of side margin layers laminated in the width direction. An outer layer portion as a region in which the plurality of internal electrodes is not provided except for the side margin portion when a section of the laminate including the laminating direction and the width direction is viewed from the length direction includes a plurality of layer-margin layers laminated in the laminating direction.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: March 21, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Daiki Fukunaga, Hideaki Tanaka, Masahiro Wakashima, Daisuke Hamada, Hironori Tsutsumi, Satoshi Maeno, Ryota Aso, Koji Moriyama, Akihiro Tsuru
  • Patent number: 11600446
    Abstract: A multilayer ceramic capacitor includes a second alloy portion including one metal element provided in a greatest amount among metal elements of an internal electrode layer, and one or more metal elements among a metal group including Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, and Y is provided between a second dielectric ceramic layer and a first internal electrode layer, and between a second dielectric ceramic layer and a second internal electrode layer, respectively.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: March 7, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yuta Kurosu, Yuta Saito, Masahiro Wakashima, Daiki Fukunaga, Yu Tsutsui
  • Patent number: 11508524
    Abstract: In a multilayer ceramic capacitor, an intersection of an interface is defined by a second dielectric ceramic layer, a first internal electrode layer or a second internal electrode layer, and a third dielectric ceramic layer, on a plane including a length direction and a width direction, the second dielectric ceramic layer and the third dielectric ceramic layer include a near intersection region at or near the intersection, and an average particle size of dielectric particles in the near intersection region is smaller than average particle sizes of dielectric particles in the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: November 22, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yuta Kurosu, Yuta Saito, Masahiro Wakashima, Daiki Fukunaga, Yu Tsutsui
  • Publication number: 20220328252
    Abstract: A method of manufacturing an electronic component includes preparing an unfired multilayer body including first and second main surfaces facing each other in a stacking direction, first and second side surfaces facing each other in a width direction, and first and second end surfaces facing each other in a length direction, bonding one main surface of the unfired multilayer body to an elongated first adhesive sheet, conveying the first adhesive sheet in a first direction in which the first adhesive sheet approaches an elongated second adhesive sheet, and bonding one side surface of the unfired multilayer body to the second adhesive sheet, conveying the second adhesive sheet in a second direction different from the first direction to peel off the unfired multilayer body from the first adhesive sheet, polishing another side surface of the unfired multilayer body, and forming a first insulating layer on the polished another side surface.
    Type: Application
    Filed: June 21, 2022
    Publication date: October 13, 2022
    Inventor: Daiki FUKUNAGA
  • Patent number: 11450484
    Abstract: In a multilayer ceramic capacitor includes, in a plane including a center portion in a length direction, and a stacking direction and a width direction of a first dielectric ceramic layer, where a thickness at a center portion in the stacking direction is T1, a thickness at an end of the first dielectric ceramic layer in the width direction is T2, and respective thicknesses between an end of a first internal electrode layer in the length direction not connected to a second external electrode, and the second external electrode, and between an end of the second internal electrode layer in the length direction not connected to the first external electrode, and the first external electrode is T3, a difference in thickness between T1 and T2 is within about 10% of T1, and a thickness of T3 is greater than T1 and T2 and a difference thereof is about 10% or more of T1 and T2.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: September 20, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masahiro Wakashima, Yuta Saito, Yuta Kurosu, Daiki Fukunaga, Yu Tsutsui