Patents by Inventor Daiki FUKUNAGA

Daiki FUKUNAGA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240087814
    Abstract: A multilayer ceramic capacitor includes a second alloy portion including one metal element provided in a greatest amount among metal elements of an internal electrode layer, and one or more metal elements among a metal group including Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, and Y is provided between a second dielectric ceramic layer and a first internal electrode layer, and between a second dielectric ceramic layer and a second internal electrode layer, respectively.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 14, 2024
    Inventors: Yuta KUROSU, Yuta SAITO, Masahiro WAKASHIMA, Daiki FUKUNAGA, Yu TSUTSUI
  • Patent number: 11875949
    Abstract: A method of manufacturing an electronic component includes preparing an unfired multilayer body including first and second main surfaces facing each other in a stacking direction, first and second side surfaces facing each other in a width direction, and first and second end surfaces facing each other in a length direction, bonding one main surface of the unfired multilayer body to an elongated first adhesive sheet, conveying the first adhesive sheet in a first direction in which the first adhesive sheet approaches an elongated second adhesive sheet, and bonding one side surface of the unfired multilayer body to the second adhesive sheet, conveying the second adhesive sheet in a second direction different from the first direction to peel off the unfired multilayer body from the first adhesive sheet, polishing another side surface of the unfired multilayer body, and forming a first insulating layer on the polished another side surface.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: January 16, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Daiki Fukunaga
  • Publication number: 20240013982
    Abstract: A multilayer ceramic capacitor includes a laminated body and first and second external electrodes respectively on both end surfaces of the laminated body. When regions where first internal electrodes or second internal electrodes are not present are regarded as side margin portions in a cross section of the laminated body as viewed from the laminating direction, the side margin portions include multiple side margin layers, and the content of Si in the side margin layer closest to the internal electrode is lower than that in the side margin layer other than the side margin layer closest to the internal electrode.
    Type: Application
    Filed: September 20, 2023
    Publication date: January 11, 2024
    Inventors: Hideaki TANAKA, Daiki FUKUNAGA, Koji MORIYAMA
  • Patent number: 11869724
    Abstract: A multilayer ceramic capacitor includes a second alloy portion including one metal element provided in a greatest amount among metal elements of an internal electrode layer, and one or more metal elements among a metal group including Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, and Y is provided between a second dielectric ceramic layer and a first internal electrode layer, and between a second dielectric ceramic layer and a second internal electrode layer, respectively.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: January 9, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yuta Kurosu, Yuta Saito, Masahiro Wakashima, Daiki Fukunaga, Yu Tsutsui
  • Patent number: 11798746
    Abstract: A multilayer ceramic capacitor includes a laminated body and first and second external electrodes respectively on both end surfaces of the laminated body. When regions where first internal electrodes or second internal electrodes are not present are regarded as side margin portions in a cross section of the laminated body as viewed from the laminating direction, the side margin portions include multiple side margin layers, and the content of Si in the side margin layer closest to the internal electrode is lower than that in the side margin layer other than the side margin layer closest to the internal electrode.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: October 24, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hideaki Tanaka, Daiki Fukunaga, Koji Moriyama
  • Patent number: 11721490
    Abstract: A method of manufacturing a multilayer ceramic capacitor includes printing an internal electrode pattern on a dielectric layer, forming a dielectric pattern in a region other than a region in which the internal electrode pattern is printed, laminating dielectric layers to form a multilayer body, exposing the internal electrode pattern and the dielectric pattern from a side surface of the multilayer body, removing at least a portion of the exposed dielectric pattern, and forming a dielectric gap layer on the side surface.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: August 8, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yu Tsutsui, Yuta Kurosu, Daiki Fukunaga, Yuta Saito, Masahiro Wakashima
  • Publication number: 20230202814
    Abstract: A transport robot is configured to transfer a transported article to and from an installed shelf by passing the installed shelf. A shelf portion that holds the transported article is configured to pass the installed shelf by the transport robot traveling. A chassis is configured to support the shelf portion. A stand is disposed on a first end portion side in a right-left direction of the transport robot, and extends upward from the chassis. An operating unit is configured to be installed on the stand.
    Type: Application
    Filed: November 10, 2022
    Publication date: June 29, 2023
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Satoshi TOYOSHIMA, Daiki FUKUNAGA, Shiro ODA, Nobuyuki TOMATSU, Keisuke FUKUNAGA, Zixun MEI, Takeshi MATSUI, Toshiyuki KAWABE
  • Publication number: 20230197340
    Abstract: An electronic component includes a laminate in which a plurality of dielectric layers and a plurality of internal electrodes are alternately laminated and external electrodes electrically connected to the internal electrodes. A side margin portion as a region in which the plurality of internal electrodes is not provided when a section of the laminate having the length direction and the width direction is viewed from the laminating direction includes a plurality of side margin layers laminated in the width direction. An outer layer portion as a region in which the plurality of internal electrodes is not provided except for the side margin portion when a section of the laminate including the laminating direction and the width direction is viewed from the length direction includes a plurality of layer-margin layers laminated in the laminating direction.
    Type: Application
    Filed: February 16, 2023
    Publication date: June 22, 2023
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Daiki FUKUNAGA, Hideaki TANAKA, Masahiro WAKASHIMA, Daisuke HAMADA, Hironori TSUTSUMI, Satoshi MAENO, Ryota ASO, Koji MORIYAMA, Akihiro TSURU
  • Publication number: 20230178305
    Abstract: A multilayer ceramic capacitor includes a second alloy portion including one metal element provided in a greatest amount among metal elements of an internal electrode layer, and one or more metal elements among a metal group including Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, and Y is provided between a second dielectric ceramic layer and a first internal electrode layer, and between a second dielectric ceramic layer and a second internal electrode layer, respectively.
    Type: Application
    Filed: January 30, 2023
    Publication date: June 8, 2023
    Inventors: Yuta KUROSU, Yuta SAITO, Masahiro WAKASHIMA, Daiki FUKUNAGA, Yu TSUTSUI
  • Patent number: 11610736
    Abstract: An electronic component includes a laminate in which a plurality of dielectric layers and a plurality of internal electrodes are alternately laminated and external electrodes electrically connected to the internal electrodes. A side margin portion as a region in which the plurality of internal electrodes is not provided when a section of the laminate having the length direction and the width direction is viewed from the laminating direction includes a plurality of side margin layers laminated in the width direction. An outer layer portion as a region in which the plurality of internal electrodes is not provided except for the side margin portion when a section of the laminate including the laminating direction and the width direction is viewed from the length direction includes a plurality of layer-margin layers laminated in the laminating direction.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: March 21, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Daiki Fukunaga, Hideaki Tanaka, Masahiro Wakashima, Daisuke Hamada, Hironori Tsutsumi, Satoshi Maeno, Ryota Aso, Koji Moriyama, Akihiro Tsuru
  • Patent number: 11600446
    Abstract: A multilayer ceramic capacitor includes a second alloy portion including one metal element provided in a greatest amount among metal elements of an internal electrode layer, and one or more metal elements among a metal group including Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, and Y is provided between a second dielectric ceramic layer and a first internal electrode layer, and between a second dielectric ceramic layer and a second internal electrode layer, respectively.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: March 7, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yuta Kurosu, Yuta Saito, Masahiro Wakashima, Daiki Fukunaga, Yu Tsutsui
  • Patent number: 11508524
    Abstract: In a multilayer ceramic capacitor, an intersection of an interface is defined by a second dielectric ceramic layer, a first internal electrode layer or a second internal electrode layer, and a third dielectric ceramic layer, on a plane including a length direction and a width direction, the second dielectric ceramic layer and the third dielectric ceramic layer include a near intersection region at or near the intersection, and an average particle size of dielectric particles in the near intersection region is smaller than average particle sizes of dielectric particles in the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: November 22, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yuta Kurosu, Yuta Saito, Masahiro Wakashima, Daiki Fukunaga, Yu Tsutsui
  • Publication number: 20220328252
    Abstract: A method of manufacturing an electronic component includes preparing an unfired multilayer body including first and second main surfaces facing each other in a stacking direction, first and second side surfaces facing each other in a width direction, and first and second end surfaces facing each other in a length direction, bonding one main surface of the unfired multilayer body to an elongated first adhesive sheet, conveying the first adhesive sheet in a first direction in which the first adhesive sheet approaches an elongated second adhesive sheet, and bonding one side surface of the unfired multilayer body to the second adhesive sheet, conveying the second adhesive sheet in a second direction different from the first direction to peel off the unfired multilayer body from the first adhesive sheet, polishing another side surface of the unfired multilayer body, and forming a first insulating layer on the polished another side surface.
    Type: Application
    Filed: June 21, 2022
    Publication date: October 13, 2022
    Inventor: Daiki FUKUNAGA
  • Patent number: 11450484
    Abstract: In a multilayer ceramic capacitor includes, in a plane including a center portion in a length direction, and a stacking direction and a width direction of a first dielectric ceramic layer, where a thickness at a center portion in the stacking direction is T1, a thickness at an end of the first dielectric ceramic layer in the width direction is T2, and respective thicknesses between an end of a first internal electrode layer in the length direction not connected to a second external electrode, and the second external electrode, and between an end of the second internal electrode layer in the length direction not connected to the first external electrode, and the first external electrode is T3, a difference in thickness between T1 and T2 is within about 10% of T1, and a thickness of T3 is greater than T1 and T2 and a difference thereof is about 10% or more of T1 and T2.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: September 20, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masahiro Wakashima, Yuta Saito, Yuta Kurosu, Daiki Fukunaga, Yu Tsutsui
  • Patent number: 11393632
    Abstract: A method of manufacturing an electronic component includes preparing an unfired multilayer body including first and second main surfaces facing each other in a stacking direction, first and second side surfaces facing each other in a width direction, and first and second end surfaces facing each other in a length direction, bonding one main surface of the unfired multilayer body to an elongated first adhesive sheet, conveying the first adhesive sheet in a first direction in which the first adhesive sheet approaches an elongated second adhesive sheet, and bonding one side surface of the unfired multilayer body to the second adhesive sheet, conveying the second adhesive sheet in a second direction different from the first direction to peel off the unfired multilayer body from the first adhesive sheet, polishing another side surface of the unfired multilayer body, and forming a first insulating layer on the polished another side surface.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: July 19, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Daiki Fukunaga
  • Patent number: 11373810
    Abstract: In a multilayer ceramic capacitor, a first segregation defined by at least one metal element selected from a group consisting of Mg, Mn, and Si is present at each of an end in a length direction of a first internal electrode layer not connected to a second external electrode and an end in a length direction of a second internal electrode layer not connected to a first external electrode. A second segregation defined by at least one metal element selected from a group consisting of Mg, Mn, and Si is present at each of an end of the first internal electrode layer in a width direction and an end of the second internal electrode layer in the width direction.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: June 28, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yuta Saito, Yuta Kurosu, Masahiro Wakashima, Daiki Fukunaga, Yu Tsutsui
  • Patent number: 11367573
    Abstract: A multilayer ceramic capacitor includes, in at least one of a region between an end of a first internal electrode layer which is not connected to a second external electrode and the second external electrode, and a region between an end of a second internal electrode layer which is not connected to a first external electrode and the first external electrode, in a length direction, a defect portion provided on a plane including a stacking direction and a width direction, such that the defect portion is located between the first dielectric ceramic layers in the stacking direction and is located between the second dielectric ceramic layer and the third dielectric ceramic layer in the width direction.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: June 21, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yu Tsutsui, Yuta Kurosu, Daiki Fukunaga, Yuta Saito, Masahiro Wakashima
  • Publication number: 20220148812
    Abstract: A method of manufacturing a multilayer ceramic capacitor includes printing an internal electrode pattern on a dielectric layer, forming a dielectric pattern in a region other than a region in which the internal electrode pattern is printed, laminating dielectric layers to form a multilayer body, exposing the internal electrode pattern and the dielectric pattern from a side surface of the multilayer body, removing at least a portion of the exposed dielectric pattern, and forming a dielectric gap layer on the side surface.
    Type: Application
    Filed: October 7, 2021
    Publication date: May 12, 2022
    Inventors: Yu TSUTSUI, Yuta KUROSU, Daiki FUKUNAGA, Yuta SAITO, Masahiro WAKASHIMA
  • Patent number: 11322307
    Abstract: A multilayer ceramic capacitor includes a third segregation by each of metal elements of a first segregation and a second segregation is provided at each of a first corner region in which an end in a length direction in which the first segregation is provided overlaps an end in a width direction in which the second segregation is provided in a first internal electrode layer, and a second corner region in which an end in the length direction in which the second segregation is provided overlaps an end in the width direction in which the second segregation is provided in a second internal electrode layer.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: May 3, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Daiki Fukunaga, Yuta Kurosu, Yuta Saito, Masahiro Wakashima, Yu Tsutsui
  • Patent number: 11239030
    Abstract: An electronic component includes a laminate including internal electrodes alternately laminated in a lamination direction with dielectric layers interposed therebetween. The laminate includes main surfaces opposite to each other in the lamination direction, side surfaces opposite to each other in a width direction, and end surfaces opposite to each other in a length direction, and external electrodes provided on surfaces of the laminate and electrically connected to the internal electrodes. Each of the dielectric layers includes Ti and Mg. When a cross section including the length direction and the width direction of the laminate is viewed from the lamination direction, side margin portions in which the internal electrodes do not exist each include a dielectric including Ti and Mg with a molar ratio in each of the side margin portions smaller than a molar ratio of Mg to Ti included in each of the dielectric layers.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: February 1, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hideyuki Hashimoto, Daiki Fukunaga, Takayuki Yao, Takehisa Sasabayashi