Abstract: A plurality of SRAM macros each including a memory cell array, an input/output circuit, a word line driver, and a control circuit are mounted on a semiconductor chip. Each of the SRAM macros includes a determination block disposed in the control circuit and configured to generate a mode signal for determining a read assist amount and a write assist amount based on a power supply voltage of the SRAM macro, and an assist circuit that performs a read assist operation and a write assist operation based on the mode signal generated by the determination block.

Abstract: A related-art semiconductor device has a problem that is a large operation error. A semiconductor device according to an embodiment includes: an input control circuit dividing a plurality of bit values representing an input value into a plurality of division values each having a predetermined number of bits, and outputting the division values; a plurality of memory units each including a plurality of memory cells each outputting a product of a held value represented by a ternary value and any one of the plurality of bit values representing the input value, each of the plurality of memory units corresponding to any one of the division values; and a sum operation circuit performing sum operation processing to an output value to be output for each of the division values, and outputting a final operation result value.

Abstract: A semiconductor device includes a first data line, a second data line, and a memory cell connected to the first data line and the second data line. The memory cell includes a plurality of switches, a first data holding circuit, a second data holding circuit, a third data holding circuit, a fourth data holding circuit, and an input line. A characteristic value of the memory cell is changeable by controlling the switch connected to the first data line among the plurality of switches based on a value held by the third data holding circuit and by controlling the switch connected to the second data line among the plurality of switches based on a value held by the fourth data holding circuit.

Abstract: In the semiconductor device according to an embodiment, a memory cell is controlled such that, for the part whose output value can be fixed based on the value stored in the memory cell without performing the information processing, the operation processing is stopped so as to stop the charging and discharging to and from the data line, and for the part whose output value needs to be fixed by performing the information processing, the information processing accompanied by charging and discharging to and from the data line is appropriately performed.

Abstract: An electronic circuit includes a cell array including memory cells each including a bistable circuit that includes first and second inverter circuits, each having a first mode characterized by there being substantially no hysteresis in transfer characteristics and a second mode characterized by there being hysteresis in the transfer characteristics, and being switchable between the first and second modes, and a control circuit configured to, after powering off a first memory cell that store data that are not required to be retained, put the bistable circuit in a remaining second memory cell into the second mode, and supply a second power supply voltage that allows the bistable circuit in the second mode to retain data and is lower than a first power supply voltage supplied to the bistable circuit when data is read and/or written, to the bistable circuit in the second memory cell while maintaining the second mode.