Patents by Inventor Daiki Moteki

Daiki Moteki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and method for designing a semiconductor device
    Patent number: 10216886
    Abstract: A semiconductor design apparatus computes a consumption current in a macro cell region in the semiconductor device. A first region is defined to be a first shape and size on an upper surface on at least one end of a one-side end portion of the macro cell region based on the consumption current in the macro cell region and an allowable current per via that connects a power supply layer and the macro cell region to each other. A second region is defined as a second shape and size on the upper surface of the macro cell region based on the first region. The apparatus determines an arrangement of the macro cell region and the power supply layer based on the second region and determines the arrangement of vias in the second region based on the arrangement of the macro cell region and the power supply layer.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: February 26, 2019
    Assignee: MegaChips Corporation
    Inventor: Daiki Moteki
  • SEMICONDUCTOR DEVICE AND METHOD FOR DESIGNING A SEMICONDUCTOR DEVICE
    Publication number: 20170357745
    Abstract: A semiconductor design apparatus computes a consumption current in a macro cell region in the semiconductor device. A first region is defined to be a first shape and size on an upper surface on at least one end of a one-side end portion of the macro cell region based on the consumption current in the macro cell region and an allowable current per via that connects a power supply layer and the macro cell region to each other. A second region is defined as a second shape and size on the upper surface of the macro cell region based on the first region. The apparatus determines an arrangement of the macro cell region and the power supply layer based on the second region and determines the arrangement of vias in the second region based on the arrangement of the macro cell region and the power supply layer.
    Type: Application
    Filed: August 3, 2017
    Publication date: December 14, 2017
    Applicant: MegaChips Corporation
    Inventor: Daiki Moteki
  • Semiconductor device and method for designing a semiconductor device
    Patent number: 9754066
    Abstract: A semiconductor design apparatus computes a consumption current in a macro cell region in the semiconductor device. A first region is defined to be a first shape and size on an upper surface on at least one end of a one-side end portion of the macro cell region based on the consumption current in the macro cell region and an allowable current per via that connects a power supply layer and the macro cell region to each other. A second region is defined as a second shape and size on the upper surface of the macro cell region based on the first region. The apparatus determines an arrangement of the macro cell region and the power supply layer based on the second region and determines the arrangement of vias in the second region based on the arrangement of the macro cell region and the power supply layer.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: September 5, 2017
    Assignee: MegaChips Corporation
    Inventor: Daiki Moteki
  • SEMICONDUCTOR DEVICE AND METHOD FOR DESIGNING A SEMICONDUCTOR DEVICE
    Publication number: 20150278424
    Abstract: A semiconductor design apparatus computes a consumption current in a macro cell region in the semiconductor device. A first region is defined to be a first shape and size on an upper surface on at least one end of a one-side end portion of the macro cell region based on the consumption current in the macro cell region and an allowable current per via that connects a power supply layer and the macro cell region to each other. A second region is defined as a second shape and size on the upper surface of the macro cell region based on the first region. The apparatus determines an arrangement of the macro cell region and the power supply layer based on the second region and determines the arrangement of vias in the second region based on the arrangement of the macro cell region and the power supply layer.
    Type: Application
    Filed: March 27, 2015
    Publication date: October 1, 2015
    Applicant: MEGACHIPS CORPORATION
    Inventor: Daiki Moteki