Abstract: A photoelectric conversion device includes a substrate and a wiring layer disposed on the substrate. The wiring layer includes a wiring structure and a wiring insulating layer that surrounds the wiring structure. A reflective layer is disposed on the wiring layer. The reflective layer is electrically connected to the wiring structure. A semi-permeable metal layer is spaced apart from the reflective layer in a thickness direction of the substrate. The semi-permeable metal layer faces the reflective layer to form a microcavity between the reflective layer and the semi-permeable metal layer. A stacked structure is between the reflective layer and the semi-permeable metal layer in the thickness direction of the substrate. The stacked structure includes a photoelectric conversion layer, a transparent electrode layer, and an insulating optical spacer.

Abstract: A semiconductor device includes an N-type fin and a P-type fin on a substrate, a first gate electrode configured to cross the N-type fin and cover a side surface of the N-type fin, a second gate electrode configured to cross the P-type fin and cover a side surface of the P-type fin, a first source/drain on the N-type fin adjacent to the first gate electrode, a second source/drain on the P-type fin adjacent to the second gate electrode, a buffer layer on a surface of the second source/drain and including a material different from the second source/drain, an interlayer insulating layer on the buffer layer and the first source/drain, a first plug connected to the first source/drain and passing through the interlayer insulating layer, and a second plug connected to the second source/drain and passing through the interlayer insulating layer and the buffer layer.

Abstract: A semiconductor device includes an N-type fin and a P-type fin on a substrate, a first gate electrode configured to cross the N-type fin and cover a side surface of the N-type fin, a second gate electrode configured to cross the P-type fin and cover a side surface of the P-type fin, a first source/drain on the N-type fin adjacent to the first gate electrode, a second source/drain on the P-type fin adjacent to the second gate electrode, a buffer layer on a surface of the second source/drain and including a material different from the second source/drain, an interlayer insulating layer on the buffer layer and the first source/drain, a first plug connected to the first source/drain and passing through the interlayer insulating layer, and a second plug connected to the second source/drain and passing through the interlayer insulating layer and the buffer layer.