Patents by Inventor Dain C. Miller

Dain C. Miller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated bipolar transistor and field effect transistor
    Patent number: 7656002
    Abstract: The present invention relates to a microelectronic device having a bipolar epitaxial structure that provides at least one bipolar transistor element formed over at least one field effect transistor (FET) epitaxial structure that provides at least one FET element. The epitaxial structures are separated with at least one separation layer. Additional embodiments of the present invention may use different epitaxial layers, epitaxial sub-layers, metallization layers, isolation layers, layer materials, doping materials, isolation materials, implant materials, or any combination thereof.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: February 2, 2010
    Assignee: RF Micro Devices, Inc.
    Inventors: Curtis A. Barratt, Michael T. Fresina, Brian G. Moser, Dain C. Miller, Walter A. Wohlmuth
  • Planar ion-implanted GaAs MESFETS with improved open-channel burnout characteristics
    Patent number: 5565696
    Abstract: An improved substantially planar and easy to manufacture field-effect-transistor (FET) includes a guard region between an n.sup.+ drain region and the remainder of the device, which enables the breakdown voltage of the FET to be substantially increased under open-channel conditions without adversely impacting other important device characteristics.
    Type: Grant
    Filed: November 21, 1995
    Date of Patent: October 15, 1996
    Assignee: ITT Corporation
    Inventors: Dain C. Miller, Robert A. Sadler, Andrew H. Peake
  • Method for fabricating a planar ion-implanted GaAs MESFET with improved open-channel burnout characteristics
    Patent number: 5536666
    Abstract: An improved substantially planar and easy to manufacture field-effect-transistor (FET) includes a guard region between an n+ drain region and the remainder of the device, which enables the breakdown voltage of the FET to be substantially increased under open-channel conditions without adversely impacting other important device characteristics.
    Type: Grant
    Filed: March 16, 1995
    Date of Patent: July 16, 1996
    Assignee: ITT Corporation
    Inventors: Dain C. Miller, Robert A. Sadler, Andrew H. Peake