Patents by Inventor Daisaku HIYAMIZU

Daisaku HIYAMIZU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuits, multi-chip package, and operation method of semiconductor integrated circuits
    Patent number: 11749355
    Abstract: According to a certain embodiment, the semiconductor integrated circuit includes a multi-chip package comprising a plurality of memory chips, and a controller configured to control the multi-chip package. Each of the plurality of memory chips includes a logic control unit including a logic unit circuit configured to detect a potential from a wiring pad. The logic unit circuit determines a master chip or a slave chip on the basis of the potential detected from the wiring pad, the master chip transmits a pulse count and a status response command to the slave chip, so that the slave chip sets a logical unit number of its own memory chip, and the master chip sets a total number of chips loaded on the basis of status information from the slave chip.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: September 5, 2023
    Assignee: Kioxia Corporation
    Inventor: Daisaku Hiyamizu
  • SEMICONDUCTOR INTEGRATED CIRCUITS, MULTI-CHIP PACKAGE, AND OPERATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUITS
    Publication number: 20220301635
    Abstract: According to a certain embodiment, the semiconductor integrated circuit includes a multi-chip package comprising a plurality of memory chips, and a controller configured to control the multi-chip package. Each of the plurality of memory chips includes a logic control unit including a logic unit circuit configured to detect a potential from a wiring pad. The logic unit circuit determines a master chip or a slave chip on the basis of the potential detected from the wiring pad, the master chip transmits a pulse count and a status response command to the slave chip, so that the slave chip sets a logical unit number of its own memory chip, and the master chip sets a total number of chips loaded on the basis of status information from the slave chip.
    Type: Application
    Filed: August 5, 2021
    Publication date: September 22, 2022
    Applicant: Kioxia Corporation
    Inventor: Daisaku HIYAMIZU