Abstract: In a method of managing an electrical device, details of at least one operation performed using any one of one or more operation terminals to operate an electrical device are stored (S800); and when a state of running of the electrical device is displayed according to the details of at least one operation that are stored (S810), (i) information indicating which one of the one or more operation terminals has been used in operating the running and (ii) information indicating whether or not the details of at least one operation for the running have been performed using, among the one or more operation terminals, one operation terminal that is present in a same home as the electrical device are presented (S820, S830).

Abstract: In an external medium communication system including a non-contact card 300, which is an external medium, and a card communication device 400, which is a communication device, the non-contact card 300 includes a conductive unit 320, and the card communication device 400 includes a detection antenna unit 420 including a detection output antenna 421 and a detection input antenna 422. When the external medium 300 is mounted in a predetermined position, the card communication device 400 detects that the non-contact card 300 is in the predetermined position by detecting that the detection output antenna 421 and the detection input antenna 422 are coupled by electromagnetic induction across the conducting unit 320.

Abstract: The present invention provides a semiconductor device capable of changing the setting of the internal operation mode without increasing the number of terminals of the semiconductor device. The semiconductor device includes a transmitting cell, a receiving cell, a semiconductor chip including a transmitting antenna and a receiving antenna, and a conductor. The transmitting antenna is connected to the transmitting cell, and the receiving antenna is connected to the receiving cell. The conductor is provided close to the transmitting antenna and the receiving antenna. Close proximity wireless communication is used between the transmitting cell and the receiving cell.

Abstract: One array antenna including three induction coils is formed on an application integrated circuit of a fixed housing. Eight array antennas, each of which is arranged in a manner similar to that of the array antennas of the application integrated circuit, are formed at intervals of 45 degrees around a rotation axis on an imaging process integrated circuit of a movable housing. A controller selects one of the eight array antennas of the imaging process integrated circuit so that a magnitude of a difference between a rotation angle of a movable housing and a rotation angle of the movable housing becomes equal to or smaller than 22.5 degrees based on the rotation angle of the movable housing, and controls a stepping motor so that a selected array antenna opposes to the array antenna on the application integrated circuit.

Abstract: In an external medium communication system including a non-contact card 300, which is an external medium, and a card communication device 400, which is a communication device, the non-contact card 300 includes a conductive unit 320, and the card communication device 400 includes a detection antenna unit 420 including a detection output antenna 421 and a detection input antenna 422. When the external medium 300 is mounted in a predetermined position, the card communication device 400 detects that the non-contact card 300 is in the predetermined position by detecting that the detection output antenna 421 and the detection input antenna 422 are coupled by electromagnetic induction across the conducting unit 320.

Abstract: The present invention provides a semiconductor device capable of changing the setting of the internal operation mode without increasing the number of terminals of the semiconductor device. The semiconductor device 100a includes a transmitting cell, a receiving cell, a semiconductor chip 120 including a transmitting antenna 121a and a receiving antenna 122a, and a conductor 111a. The transmitting antenna 121a is connected to the transmitting cell, and the receiving antenna 122a is connected to the receiving cell. The conductor 111a is provided close to the transmitting antenna 121a and the receiving antenna 122a. Close proximity wireless communication is used between the transmitting cell and the receiving cell.

Abstract: After reading data from a memory in response to a read request received from a bus master and burst transferring the read data, a memory interface 100 continues to read and store (i.e., continuously reads and stores) data starting from an address that follows all of addresses of the read data. Upon receiving a new read request from the bus master within a predetermined time, the memory interface 100 determines whether a difference between an address specified by a previous read request and an address specified by a new read request falls within a predetermined range. If it is determined positively, the memory interface 100 successively transfers the stored data in response to the new read request. If it is determined negatively, or if the reception of the new read request is not performed within the predetermined time, the memory interface 100 terminates the continuous data read.

Abstract: One array antenna including three induction coils is formed on an application integrated circuit of a fixed housing. Eight array antennas, each of which is arranged in a manner similar to that of the array antennas of the application integrated circuit, are formed at intervals of 45 degrees around a rotation axis on an imaging process integrated circuit of a movable housing. A controller selects one of the eight array antennas of the imaging process integrated circuit so that a magnitude of a difference between a rotation angle of a movable housing and a rotation angle of the movable housing becomes equal to or smaller than 22.5 degrees based on the rotation angle of the movable housing, and controls a stepping motor so that a selected array antenna opposes to the array antenna on the application integrated circuit.

Abstract: A cryptographic processing device 100 includes an interruption timing judgment circuit 101. The interruption timing judgment circuit 101 includes an interruption timing judgment register 101a, a transfer state reference unit 101b, and an interruption timing judgment unit 101c. The interruption timing judgment register 101a stores a table 200 used by the interruption timing judgment unit 101c to judge whether to interrupt transfer performed by a DMAC 102. The transfer state reference unit 101b monitors how many bytes among blocks read from a memory 14 the DMAC 102 has input into a cryptographic computing circuit 103. The interruption timing judgment unit 101c judges whether to switch a transfer target during transfer of image data by the DMAC 102, based on the table 200 stored in the interruption timing judgment register 101a and a result of the monitoring by the transfer state reference unit 101b (i.e. the number of transferred bytes).

Abstract: Even after reading data from a memory in response to a read request received from a bus master and burst transferring the read data, the memory interface 100 continues to read and store data starting from an address that follows all of addresses of the read data. Upon receiving a new read request from the bus master within a predetermined time, the memory interface 100 determines whether a difference between the address specified by the previous read request and the address specified by the new read request falls within a predetermined range. If it is determined positively, the memory interface 100 successively transfers the stored data in response to the new read request. If it is determined negatively, or if the reception of the new read request is not performed within the predetermined time, the memory interface 100 terminates the continuous data read.

Abstract: A cryptographic processing device 100 includes an interruption timing judgment circuit 101. The interruption timing judgment circuit 101 includes an interruption timing judgment register 101a, a transfer state reference unit 101b, and an interruption timing judgment unit 101c. The interruption timing judgment register 101a stores a table 200 used by the interruption timing judgment unit 101c to judge whether to interrupt transfer performed by a DMAC 102. The transfer state reference unit 101b monitors how many bytes among blocks read from a memory 14 the DMAC 102 has input into a cryptographic computing circuit 103. The interruption timing judgment unit 101c judges whether to switch a transfer target during transfer of image data by the DMAC 102, based on the table 200 stored in the interruption timing judgment register 101a and a result of the monitoring by the transfer state reference unit 101b (i.e. the number of transferred bytes).

Abstract: The present invention provides a dividing method taking, into consideration, memory access when determining vertices of polygons created through division in an image rendering apparatus for rendering a 3-dimensional image with polygons, in which a polygon is divided into smaller polygons in order to improve the representational power of an image. The image rendering apparatus according to the present invention can write pixel data for an image that is to be displayed to a frame memory in the unit of a predetermined number of pixels. The image rendering apparatus selects vertices of polygons created through division such that the vertices are at the first pixel or the last pixel in the writing pixel unit.

Abstract: The present invention aims at, as to a drawing apparatus that stores an image in the frame memory via the cache memory, shortening the time period required for storing an entire image data in the frame memory. In the case where the frame memory is sectionalized in increments of the unit of pixels burst-transferred from the cache memory to the frame memory when partial data pieces of the image data to be eventually stored in the frame memory are stored in the cache memory, the drawing apparatus stores pixel data pieces for each sectionalized area in the cache memory in a manner that the cache memory needs to access the frame memory only once for each sectionalized area.

Abstract: The present invention provides a dividing method taking, into consideration, memory access when determining vertices of polygons created through division in an image rendering apparatus for rendering a 3-dimensional image with polygons, in which a polygon is divided into smaller polygons in order to improve the representational power of an image. The image rendering apparatus according to the present invention can write pixel data for an image that is to be displayed to a frame memory in the unit of a predetermined number of pixels. The image rendering apparatus selects vertices of polygons created through division such that the vertices are at the first pixel or the last pixel in the writing pixel unit.

Abstract: An image display control apparatus having a small-size circuit includes: an image state detection unit for detecting a state of an image based on an image signal using a resource subunit in a resource unit; an image signal transformation unit for transforming the image signal, using the resource subunit in the resource unit, based on the state of the image detected by the image state detection unit; and a resource control unit for assigning the resource subunit in the resource unit to each of the image state detection unit and the image signal transformation unit according to a count number of cycles of an operation clock outputted from a clock unit.

Abstract: The present invention aims at, as to a drawing apparatus that stores an image in the frame memory via the cache memory, shortening the time period required for storing an entire image data in the frame memory. In the case where the frame memory is sectionalized in increments of the unit of pixels burst-transferred from the cache memory to the frame memory when partial data pieces of the image data to be eventually stored in the frame memory are stored in the cache memory, the drawing apparatus stores pixel data pieces for each sectionalized area in the cache memory in a manner that the cache memory needs to access the frame memory only once for each sectionalized area.

Abstract: An image object content generation device has a key generation unit that generates a key that is a reference for distinguishing an object pixel from a background pixel per pixel of an inputted image signal, a frame size changing unit that changes a frame size of the image signal, and a low frequency component passing unit that removes high frequency components of the image signal which was processed in the frame size changing unit. The image object generation device also has a pixel compensation unit that performs a padding processing to the image signal which was processed in the low frequency component passing unit by using Low Pass Extrapolation padding algorithm, and a pixel selecting unit that selects one of the Image signal which was processed in the low frequency component passing unit and the image signal which was processed in the pixel compensation unit.

Abstract: An image display control apparatus 103 having a small-size circuit includes: an image state detection unit 120 for detecting a state of an image based on an image signal using a resource subunit 610 in a resource unit 132; an image signal transformation unit 140 for transforming the image signal, using the resource subunit 610 in the resource unit 132, based on the state of the image detected by the image state detection unit 120; and a resource control unit 131 for assigning the resource subunit 610 in the resource unit 132 to each of the image state detection unit 120 and the image signal transformation unit 140 according to a count number of cycles of an operation clock outputted from a clock unit 135.

Abstract: An image object content generation device 10 comprises a key generation unit 11 that generates a key that is a reference for distinguishing an object pixel from a background pixel per pixel of an inputted image signal, a frame size changing unit 12 that changes a frame size of the image signal, a low frequency component passing unit 13 that removes high frequency components of the image signal which was processed in the frame size changing unit 12, a pixel compensation unit 14 that performs a padding processing to the image signal which was processed in the low frequency component passing unit 13 by using Low Pass Extrapolation padding algorithm, and a pixel selecting unit 15 that selects one of the image signal which was processed in the low frequency component passing unit 13 and the image signal which was processed in the pixel compensation unit 14.