Patents by Inventor Daishi Tanabe

Daishi Tanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220232672
    Abstract: An electrode-embedded ceramic structure includes: a ceramic shaft, wherein an electrode is disposed on an outer circumference thereof; and a ceramic tube housing the ceramic shaft therein and coupled to the ceramic shaft. In this electrode-embedded ceramic structure, spaces are provided locally between the ceramic shaft and the ceramic tube.
    Type: Application
    Filed: April 4, 2022
    Publication date: July 21, 2022
    Applicant: NGK Insulators, Ltd.
    Inventors: Takao OHNISHI, Daishi TANABE, Akifumi MORISHITA
  • Publication number: 20220214205
    Abstract: An electrode embedded ceramic structure includes: a first ceramic layer; an electrode layer formed on the first ceramic layer; and a second ceramic layer covering the first ceramic layer and the electrode layer, the second ceramic layer being thinner than the first ceramic layer. In a cross section of the first ceramic layer, the electrode layer, and the second ceramic layer along a laminating direction in this electrode embedded ceramic structure, T1 and T2 satisfy Equation (T2?T1)/T2?0.15, where T1 denotes a least thickness in the second ceramic layer, and T2 denotes an average thickness of the second ceramic layer.
    Type: Application
    Filed: March 25, 2022
    Publication date: July 7, 2022
    Applicant: NGK Insulators, Ltd.
    Inventors: Takao OHNISHI, Daishi TANABE, Akifumi MORISHITA
  • Publication number: 20220214204
    Abstract: An electrode embedded ceramic structure includes: a first ceramic layer; an electrode layer formed on the first ceramic layer; and a second ceramic layer covering the first ceramic layer and the electrode layer, the second ceramic layer being thinner than the first ceramic layer. In a cross section of the first ceramic layer, the electrode layer, and the second ceramic layer along a laminating direction in this electrode embedded ceramic structure, L1, L2, and L3 satisfy (L1+L2)/L3?2.2, where L1 denotes a length of the electrode layer on the first ceramic layer, L2 denotes a length of the electrode layer on the second ceramic layer, and L3 denotes a length of the electrode layer in a direction orthogonal to the laminating direction.
    Type: Application
    Filed: March 25, 2022
    Publication date: July 7, 2022
    Applicant: NGK Insulators, Ltd.
    Inventors: Takao OHNISHI, Daishi TANABE, Akifumi MORISHITA
  • Patent number: 8421215
    Abstract: In the laminated and sintered ceramic circuit board according to the present invention, at least a portion of the inplane conductor is fine-lined, such that the shape of the cross-section surface of the fine-lined inplane conductor is trapezoid, and the height (a), the length (c) of the lower base and the length (d) of the upper base of the trapezoidal cross-section surfaces, and the interval (b) between the lower bases of the trapezoidal cross-section surfaces of the inplane conductors adjacent in a plane parallel to the principal surfaces of the board meet a certain relation. This provides a laminated ceramic circuit board with low open failure rate, short-circuit failure rate and high reliability against high temperature and high humidity in a downsized and short-in-height (thin) semiconductor package.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: April 16, 2013
    Assignee: NGK Insulators, Ltd.
    Inventors: Makoto Tani, Takami Hirai, Shinsuke Yano, Daishi Tanabe
  • Publication number: 20130049202
    Abstract: In the laminated and sintered ceramic circuit board according to the present invention, at least a portion of the inplane conductor is fine-lined, such that the shape of the cross-section surface of the fine-lined inplane conductor is trapezoid, and the height (a), the length (c) of the lower base and the length (d) of the upper base of the trapezoidal cross-section surfaces, and the interval (b) between the lower bases of the trapezoidal cross-section surfaces of the inplane conductors adjacent in a plane parallel to the principal surfaces of the board meet a certain relation. This provides a laminated ceramic circuit hoard with low open failure rate, short-circuit failure rate and high reliability against high temperature and high humidity in a downsized and short-in-height (thin) semiconductor package.
    Type: Application
    Filed: December 20, 2011
    Publication date: February 28, 2013
    Applicant: NGK Insulators, Ltd.
    Inventors: Makoto TANI, Takami Hirai, Shinsuke Yano, Daishi Tanabe