Patents by Inventor Daishin Itagaki

Daishin Itagaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8312408
    Abstract: A layout region in which a wiring pattern and a special pattern are placed is divided into division regions. The minimum pitch for the special pattern is larger than the minimum pitch for the wiring pattern. With respect to each division region, the special pattern included in a predetermined region surrounding the each division region is extracted as a peripheral pattern, and a dummy pattern placement region included in the each division region is determined. The dummy pattern placement region is apart from at least one of boundaries between adjacent division regions. A dummy pattern is added in the dummy pattern placement region with avoiding a design rule error with the peripheral pattern existing around the each division region. Then, the plurality of division regions to which the dummy pattern is added are coupled with each other.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Daishin Itagaki
  • Patent number: 8032856
    Abstract: A method of designing a semiconductor integrated circuit, includes dividing a layout area in which a wiring pattern is disposed, into a plurality of division areas, determining a dummy pattern disposition area provided in each of the plurality of division areas, adding a dummy pattern to the dummy pattern disposition area of each of the plurality of division areas, and combining division areas to which the dummy pattern is added. The dummy pattern disposition area is arranged away from at least one of boundaries between a corresponding division area of the plurality of division areas and adjacent division areas.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: October 4, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Daishin Itagaki
  • Patent number: 7877709
    Abstract: A method of placing wires for placing a shield wire with respect to a shield subject wire placed on a chip, a method includes setting a plurality of wire tracks on the chip, dividing the chip into at least a first area and a second area according to a division boundary, confirming whether the shield subject wire exists around the division boundary in the second area when the division boundary is not laid on top of the wire track, and determining whether to place the shield wire on a wire track being adjacent to division boundary in the first area based on the confirming.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: January 25, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Daishin Itagaki
  • Publication number: 20100306727
    Abstract: A layout region in which a wiring pattern and a special pattern are placed is divided into division regions. The minimum pitch for the special pattern is larger than the minimum pitch for the wiring pattern. With respect to each division region, the special pattern included in a predetermined region surrounding the each division region is extracted as a peripheral pattern, and a dummy pattern placement region included in the each division region is determined. The dummy pattern placement region is apart from at least one of boundaries between adjacent division regions. A dummy pattern is added in the dummy pattern placement region with avoiding a design rule error with the peripheral pattern existing around the each division region. Then, the plurality of division regions to which the dummy pattern is added are coupled with each other.
    Type: Application
    Filed: May 24, 2010
    Publication date: December 2, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Daishin Itagaki
  • Publication number: 20090055792
    Abstract: A method of designing a semiconductor integrated circuit, includes dividing a layout area in which a wiring pattern is disposed, into a plurality of division areas, determining a dummy pattern disposition area provided in each of the plurality of division areas, adding a dummy pattern to the dummy pattern disposition area of each of the plurality of division areas, and combining division areas to which the dummy pattern is added. The dummy pattern disposition area is arranged away from at least one of boundaries between a corresponding division area of the plurality of division areas and adjacent division areas.
    Type: Application
    Filed: July 15, 2008
    Publication date: February 26, 2009
    Inventor: Daishin Itagaki
  • Publication number: 20080233732
    Abstract: A method of placing wires for placing a shield wire with respect to a shield subject wire placed on a chip, a method includes setting a plurality of wire tracks on the chip, dividing the chip into at least a first area and a second area according to a division boundary, confirming whether the shield subject wire exists around the division boundary in the second area when the division boundary is not laid on top of the wire track, and determining whether to place the shield wire on a wire track being adjacent to division boundary in the first area based on the confirming.
    Type: Application
    Filed: March 14, 2008
    Publication date: September 25, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Daishin ITAGAKI