Abstract: A semiconductor device including: a first pad to receive first and second test commands supplied from the outside; a voltage generator circuit to generate a test target voltage on the basis of the first and second test commands; a second pad to receive first and second monitor voltages supplied from the outside in response to respective of the first and second test commands, the first and second monitor voltages corresponding to respective lower and upper limit voltages of the test target voltage; and a comparator to output a first output signal at one of first and second logical levels by comparing the test target voltage with the first monitor voltage, and to output a second output signal at one of the first and second logical levels by comparing the test target voltage with the second monitor voltage.