Abstract: A forceps system includes a forceps manipulator and a control unit. The forceps manipulator includes a forceps tip unit capable of bending with two degrees of freedom including a bending direction and a bending angle, a drive unit that generates a driving force for the forceps tip unit, an operation unit for instructing the bending direction and the bending angle, and a first detection unit that detects an angle in a rotation direction with respect to an axis of the drive transmitting unit. The control unit that controls the drive unit such that the forceps tip unit bends depending on a predetermined target bending direction and a predetermined target bending angle. The control unit sets a target bending direction on the basis of the bending direction instructed from the operation unit and the angle detected by the first detection unit.

Abstract: A forceps system includes a forceps manipulator and a control unit. The forceps manipulator includes a forceps tip unit capable of bending with two degrees of freedom including a bending direction and a bending angle, a drive unit that generates a driving force for the forceps tip unit, an operation unit for instructing the bending direction and the bending angle, and a first detection unit that detects an angle in a rotation direction with respect to an axis of the drive transmitting unit. The control unit that controls the drive unit such that the forceps tip unit bends depending on a predetermined target bending direction and a predetermined target bending angle. The control unit sets a target bending direction on the basis of the bending direction instructed from the operation unit and the angle detected by the first detection unit.

Abstract: The present invention prevents, at high speed, a malfunction from occurring at the time of changing a mode in a processor, in which information to be decoded varies with modes. The processor is provided with a circuit for referring to a result of decoding information or issuing an instruction when a write operation is performed on a register for storing data containing a bit that indicates a current mode, and for outputting a purge signal if the result of decoding information or issuing an instruction is information represented by a mode switching signal. Thus, when a mode switching signal is written to the register, a purge signal is outputted to a cache memory. Consequently, the valid bit of prefetched cache data is turned off. This prevents prefetched data from being decoded in a different mode. As a result, operations are normally performed after the switching of the mode. Alternatively, the purge signal is outputted by detecting a change in the value of the bit indicating the current mode.

Abstract: A processor is adapted to support a complex instruction set without making major modifications to the existing hardware but by adding just a few controls and thereby emulating instructions in hardware. The processor is implemented by adding, to the existing processor, a second instruction decoder for decoding an expanded instruction code not capable of issuing an instruction per cycle, and for issuing one instruction per cycle by translating the expanded instruction code into a sequence of basic instructions; a counter for counting the number of instructions to be issued by the second instruction decoder, and for outputting a signal indicating that the expanded instruction code is being executed; and an instruction selection unit for selecting the instruction issued from the first instruction decoder when executing a basic instruction code and the instruction issued from the second instruction decoder when executing the expanded instruction code.