Patents by Inventor Daisuke Chino
Daisuke Chino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12132063Abstract: Electromagnetic noise is inhibited in a semiconductor package provided with rewiring. The semiconductor package includes a semiconductor integrated circuit, wiring, and a ferromagnetic material. In addition, in the semiconductor package including the semiconductor integrated circuit, the wiring, and the ferromagnetic material, the wiring connects the semiconductor integrated circuit to a predetermined external terminal. Further, in the semiconductor package including the semiconductor integrated circuit, the wiring, and the ferromagnetic material, the ferromagnetic material is provided between the wiring and the semiconductor integrated circuit.Type: GrantFiled: April 8, 2020Date of Patent: October 29, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Masami Suzuki, Daisuke Chino
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Patent number: 11942495Abstract: A semiconductor device includes a semiconductor chip, a circuit board, a heat releasing plate, an adhesive member, and a conductive member. The circuit board transmits a signal of the semiconductor chip. The heat releasing plate has the semiconductor chip disposed thereon, and has an opening in a region on the outer side of a semiconductor chip placement region that is a region in which the semiconductor chip is disposed. The adhesive member is disposed in a region on the outer side of the opening on a different surface of the heat releasing plate from the surface on which the semiconductor chip is disposed, and bonds the circuit board and the heat releasing plate to each other. The conductive member connects the semiconductor chip and the circuit board to each other via the opening.Type: GrantFiled: June 21, 2019Date of Patent: March 26, 2024Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Daisuke Chino, Hiroyuki Shigeta, Shigekazu Ishii, Koyo Hosokawa, Hirohisa Yasukawa, Mitsuhito Kanatake, Kosuke Hareyama, Yutaka Ootaki, Kiyohisa Sakai, Atsushi Tsukada, Hirotaka Kobayashi, Ninao Sato, Yuki Yamane
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Publication number: 20220415937Abstract: Alignment accuracy between an imaging element and a filming lens is improved. An imaging apparatus includes an imaging element, a wiring substrate, a sealing section, and fitting sections. The imaging element includes an imaging chip and pads. A light transmission section that transmits incident light is arranged on the imaging chip, and the imaging chip generates an image signal on the basis of the incident light that has transmitted through the light transmission section. The pads are arranged on a bottom surface of the imaging chip which is a surface different from the surface on which the light transmission section is arranged and convey the generated image signal. The wiring substrate includes wiring that is connected to the pads, and the imaging element is arranged on a front surface of the wiring substrate. The sealing section is arranged adjacent to side surfaces of the imaging chip which are the surfaces adjacent to the bottom surface of the imaging chip and seals the imaging chip.Type: ApplicationFiled: September 30, 2020Publication date: December 29, 2022Inventors: MUTSUO TSUJI, DAISUKE CHINO
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Publication number: 20220271068Abstract: Electromagnetic noise is inhibited in a semiconductor package provided with rewiring. The semiconductor package includes a semiconductor integrated circuit, wiring, and a ferromagnetic material. In addition, in the semiconductor package including the semiconductor integrated circuit, the wiring, and the ferromagnetic material, the wiring connects the semiconductor integrated circuit to a predetermined external terminal. Further, in the semiconductor package including the semiconductor integrated circuit, the wiring, and the ferromagnetic material, the ferromagnetic material is provided between the wiring and the semiconductor integrated circuit.Type: ApplicationFiled: April 8, 2020Publication date: August 25, 2022Inventors: MASAMI SUZUKI, DAISUKE CHINO
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Publication number: 20210392253Abstract: To prevent a short circuit in an imaging element in which an electromagnetic shield is arranged. The imaging element is an imaging element including the electromagnetic shield and an adhesive. The electromagnetic shield is an electromagnetic shield that is arranged between a wiring and an imaging chip in a package that has the wiring inside and is provided with a recess for mounting the imaging chip. Furthermore, the adhesive is an adhesive used for mounting the imaging chip. Furthermore, the adhesive is arranged to cover the electromagnetic shield.Type: ApplicationFiled: September 3, 2019Publication date: December 16, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Kiyotaka HORI, Daisuke CHINO
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Publication number: 20210233949Abstract: Deformation of a semiconductor chip is to be prevented in a semiconductor device in which a heat releasing plate and a circuit board are disposed. The semiconductor device includes the semiconductor chip, the circuit board, the heat releasing plate, an adhesive member, and a conductive member. The circuit board transmits a signal of the semiconductor chip. The heat releasing plate has the semiconductor chip disposed thereon, and has an opening in a region on the outer side of a semiconductor chip placement region that is a region in which the semiconductor chip is disposed. The adhesive member is disposed in a region on the outer side of the opening on a different surface of the heat releasing plate from the surface on which the semiconductor chip is disposed, and bonds the circuit board and the heat releasing plate to each other. The conductive member connects the semiconductor chip and the circuit board to each other via the opening.Type: ApplicationFiled: June 21, 2019Publication date: July 29, 2021Inventors: DAISUKE CHINO, HIROYUKI SHIGETA, SHIGEKAZU ISHII, KOYO HOSOKAWA, HIROHISA YASUKAWA, MITSUHITO KANATAKE, KOSUKE HAREYAMA, YUTAKA OOTAKI, KIYOHISA SAKAI, ATSUSHI TSUKADA, HIROTAKA KOBAYASHI, NINAO SATO, YUKI YAMANE
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Patent number: 10332826Abstract: A semiconductor device including a plurality of solder balls on a surface the semiconductor device, and a retaining body associated with a first solder ball of the plurality of solder balls, separating the first solder ball from at least a second solder ball of the plurality of solder balls. The retaining body includes a conductive portion and an insulating portion configured to cover the conductive portion. Also, a method of manufacturing a semiconductor device, including acts of forming a plurality of retaining bodies on a surface of a wiring substrate, each retaining body comprising a conductive portion and an insulating portion covering the conductive portion, each retaining body forming an opening section, and forming a solder ball in the opening section formed by each of the retaining bodies.Type: GrantFiled: February 27, 2014Date of Patent: June 25, 2019Assignee: Sony CorporationInventors: Kosuke Hareyama, Daisuke Chino, Yuuji Nishitani
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Patent number: 10071462Abstract: To cut out a hard-brittle substrate by blasting, laying out substrates 2 on a plate material 1 made of a hard-brittle material with leaving a space for blasting; forming first protective films 4 on both surfaces of the plate material 1 at layout positions of the substrates 2; and forming second protective films 5 on both surfaces of a margin 3 of the plate material 1 with leaving a space with respect to the first protective films 4 and having outer edges from a periphery of the plate material 1 at a width of 5 mm or less; cutting regions 6 between the films 4, 4 and between the films 4, 5 from one surface of the plate material 1 to a depth of approximately half of a thickness thereof by blasting, then cutting from the other surface of the plate material 1 until the plate material 1 is penetrated.Type: GrantFiled: April 5, 2016Date of Patent: September 11, 2018Assignee: FUJI MANUFACTURING CO., LTD.Inventors: Keiji Mase, Daisuke Chino, Masato Hinata
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Publication number: 20160243673Abstract: To cut out a bard-brittle substrate by blasting, laying out substrates 2 on a plate material 1 made of a hard-brittle material with leaving a space for blasting; forming first protective films 4 on both surfaces of the plate material 1 at layout positions of the substrates 2 and forming second protective films 5 on both surfaces of a margin 3 of the plate material 1 with leaving a space with respect to the first protective films 4 and having outer edges from a periphery of the plate material 1 at a width of 5 mm or less; cutting regions 6 between the films 4, 4 and between the films 4, 5 from one surface of the plate material 1 to a depth of approximately half of a thickness thereof by blasting, then cutting from the other surface of the plate material 1 until the plate material 1 is penetrated.Type: ApplicationFiled: April 5, 2016Publication date: August 25, 2016Inventors: Keiji Mase, Daisuke Chino, Masato Hinata
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Patent number: 9333624Abstract: To cut out a hard-brittle substrate by blasting, laying out substrates 2 on a plate material 1 made of a hard-brittle material with leaving a space for blasting; forming first protective films 4 on both surfaces of the plate material 1 at layout positions of the substrates 2; and forming second protective films 5 on both surfaces of a margin 3 of the plate material 1 with leaving a space with respect to the first protective films 4 and having outer edges from a periphery of the plate material 1 at a width of 5 mm or less; cutting regions 6 between the films 4, 4 and between the films 4, 5 from one surface of the plate material 1 to a depth of approximately half of a thickness thereof by blasting, then cutting from the other surface of the plate material 1 until the plate material 1 is penetrated.Type: GrantFiled: May 1, 2013Date of Patent: May 10, 2016Assignee: FUJI MANUFACTURING CO., LTDInventors: Keiji Mase, Daisuke Chino, Masato Hinata
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Publication number: 20150380347Abstract: A semiconductor device including a plurality of solder balls on a surface the semiconductor device, and a retaining body associated with a first solder ball of the plurality of solder balls, separating the first solder ball from at least a second solder ball of the plurality of solder balls. The retaining body includes a conductive portion and an insulating portion configured to cover the conductive portion. Also, a method of manufacturing a semiconductor device, including acts of forming a plurality of retaining bodies on a surface of a wiring substrate, each retaining body comprising a conductive portion and an insulating portion covering the conductive portion, each retaining body forming an opening section, and forming a solder ball in the opening section formed by each of the retaining bodies.Type: ApplicationFiled: February 27, 2014Publication date: December 31, 2015Applicant: SONY CORPORATIONInventors: Kosuke Hareyama, Daisuke Chino, Yuuji Nishitani
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Publication number: 20130303053Abstract: To cut out a hard-brittle substrate by blasting, laying out substrates 2 on a plate material 1 made of a hard-brittle material with leaving a space for blasting; forming first protective films 4 on both surfaces of the plate material 1 at layout positions of the substrates 2; and forming second protective films 5 on both surfaces of a margin 3 of the plate material 1 with leaving a space with respect to the first protective films 4 and having outer edges from a periphery of the plate material 1 at a width of 5 mm or less; cutting regions 6 between the films 4, 4 and between the films 4, 5 from one surface of the plate material 1 to a depth of approximately half of a thickness thereof by blasting, then cutting from the other surface of the plate material 1 until the plate material 1 is penetrated.Type: ApplicationFiled: May 1, 2013Publication date: November 14, 2013Applicant: FUJI MANUFACTURING CO., LTDInventors: Keiji Mase, Daisuke Chino, Masato Hinata
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Patent number: 7739868Abstract: A deterioration diagnostic system of an exhaust gas purifying catalyst includes: an upstream side switching frequency calculator calculating the number of times of switching on the upstream side; a reference value calculator calculating a downstream side rich/lean determination level having a first width; a downstream side rich/lean determination level adjuster setting the first width to a second larger width when the number of times of switching on the upstream side is smaller than a predetermined value; a downstream side switching frequency calculator calculating the number of times of switching on the downstream side; a frequency ratio calculator calculating a frequency ratio between the number of times of switching on the downstream side and the number of times of switching on the upstream side; and a deterioration determiner determining the deterioration of the exhaust gas purifying catalyst when the frequency ratio is larger than a predetermined value.Type: GrantFiled: May 8, 2007Date of Patent: June 22, 2010Assignee: Mitsubishi Jidosha Kogyo Kabushiki KaishaInventors: Daisuke Chino, Kenji Saito, Hitoshi Kamura
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Patent number: 7565901Abstract: When the opening angle of an intake control valve is limited to a given opening angle by fuel cut, an EGR apparatus is activated, and a malfunction of the EGR apparatus is diagnosed on the basis of a change in intake manifold pressure before and after the activation of the EGR apparatus. When the control for reducing the intake-manifold negative pressure is not implemented, the change of the intake manifold pressure is corrected with a changing amount of first reference intake pressure (P(Ne)) changed by engine speed Ne. When the control for reducing the intake manifold genitive pressure is implemented, the change of the intake manifold pressure is corrected with a changing amount of second reference intake pressure (PL(Ne)) changed by engine speed Ne.Type: GrantFiled: February 11, 2008Date of Patent: July 28, 2009Assignee: Mitsubishi Jidosha Kogyo Kabushiki KaishaInventors: Katsuhiro Furuta, Daisuke Chino, Kenji Saito, Hitoshi Kamura, Akihiro Iwama, Akira Tsunooka
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Publication number: 20080202482Abstract: When the opening angle of an intake control valve is limited to a given opening angle by fuel cut, an EGR apparatus is activated, and a malfunction of the EGR apparatus is diagnosed on the basis of a change in intake manifold pressure before and after the activation of the EGR apparatus. When the control for reducing the intake-manifold negative pressure is not implemented, the change of the intake manifold pressure is corrected with a changing amount of first reference intake pressure (P(Ne)) changed by engine speed Ne. When the control for reducing the intake manifold genitive pressure is implemented, the change of the intake manifold pressure is corrected with a changing amount of second reference intake pressure (PL(Ne)) changed by engine speed Ne.Type: ApplicationFiled: February 11, 2008Publication date: August 28, 2008Inventors: Katsuhiro Furuta, Daisuke Chino, Kenji Saito, Hitoshi Kamura, Akihiro Iwama, Akira Tsunooka
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Publication number: 20070261390Abstract: A deterioration diagnostic system of an exhaust gas purifying catalyst includes: an upstream side switching frequency calculator calculating the number of times of switching on the upstream side; a reference value calculator calculating a downstream side rich/lean determination level having a first width; a downstream side rich/lean determination level adjuster setting the first width to a second width larger than the first width when the number of times of switching on the upstream side is smaller than a predetermined value; a downstream side switching frequency calculator calculating the number of times of switching on the downstream side; an intake air volume calculator calculating an intake air volume; a frequency ratio calculator calculating a frequency ratio between the number of times of switching on the downstream side and the number of times of switching on the upstream side; and a deterioration determiner determining the deterioration of the exhaust gas purifying catalyst when the frequency ratio isType: ApplicationFiled: May 8, 2007Publication date: November 15, 2007Inventors: Daisuke Chino, Kenji Saito, Hitoshi Kamura