Patents by Inventor Daisuke Fukuda

Daisuke Fukuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120323526
    Abstract: A polishing estimation/evaluation device includes a dividing unit, an overpolished area extracting unit, and a dummy modifying unit. The dividing unit divides a layout of an integrated circuit into a plurality of partial areas. The overpolished area extracting unit refers to an overpolishing condition indicating whether overpolishing occurs in a vicinity of a partial area based on a wiring density in the partial area and a wiring density in surrounding areas of the partial area, and extracts a partial area where the overpolishing occurs from the plurality of partial areas obtained by the division by the dividing unit. The dummy modifying unit modifies dummy wiring in the partial area where the overpolishing occurs extracted by the overpolished area extracting unit and/or dummy wiring in surrounding areas of the partial area to reduce the number of partial areas where the overpolishing occurs.
    Type: Application
    Filed: August 24, 2012
    Publication date: December 20, 2012
    Applicant: Fujitsu Limited
    Inventor: Daisuke FUKUDA
  • Patent number: 8238077
    Abstract: A dielectric ceramic exhibiting a high dielectric constant is provided. The relative dielectric constant of the dielectric ceramic is stable with respect to temperature dependence and exhibits insulation resistance having a reduced voltage dependence. The dielectric ceramic of the invention can be used to form a multilayer ceramic capacitor that has a long life.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: August 7, 2012
    Assignee: Kyocera Corporation
    Inventors: Youichi Yamazaki, Hideyuki Osuzu, Yoshihiro Fujioka, Daisuke Fukuda
  • Patent number: 8219375
    Abstract: A computer readable recording medium stores therein a plated film thickness calculating program for a semiconductor integrated circuit producing process in which a plating treatment, a polishing treatment and an over-polishing treatment are performed. The plated film thickness calculating program performing a process includes simulating the plating treatment of plating the surface of the substrate for a given thickness of the conductor; calculating a thickness of the conductor to be removed by the polishing treatment until at least a part of the plateaus appears; calculating a maximum thickness of the conductor to be remained on any part of the plateaus after performing the polishing treatment; and repeating the simulating, the thickness calculation and the maximum thickness calculation by changing the given thickness until a minimum of the given thickness is determined in which the maximum thickness of the remaining conductor becomes less than a predetermined level.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: July 10, 2012
    Assignee: Fujitsu Limited
    Inventor: Daisuke Fukuda
  • Patent number: 8208240
    Abstract: A crystal constituting a dielectric porcelain, comprised of a first crystal group composed of crystal grains of 0.2 atomic % or less calcium concentration and a second crystal group composed of crystal grains of 0.4 atomic % or more calcium concentration, wherein the ratio of concentration of each of magnesium and a first rare earth element contained in a center portion to that contained in a surface layer portion of crystal grains constituting the first crystal group is greater than the corresponding concentration ratio of crystal grains constituting the second crystal group, and wherein on a polished surface resulting from polishing of the surface of the dielectric porcelain, when the area of crystal grains of the first crystal group is referred to as a and the area of crystal grains of the second crystal group referred to as b, the ratio of b/(a+b) is in the range of 0.5 to 0.8.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: June 26, 2012
    Assignee: Kyocera Corporation
    Inventors: Youichi Yamazaki, Hideyuki Osuzu, Yoshihiro Fujioka, Daisuke Fukuda
  • Patent number: 8154851
    Abstract: A dielectric ceramic includes primary crystal grains. The primary crystal grains include a composite oxide of Ti and at least one kind of alkaline earth metal element selected from Ca, Sr and Ba. The primary crystal grains contain metal compositions of Mg, Mn and a rare earth element. At least one of the metal composition of the Mg, the Mn and the rare earth element is present at a higher concentration on the surface side of the primary crystal grains than the inside thereof. A 0.04 to 0.2 parts by mass of Zr in terms of oxide to 100 parts by mass of the composite oxide is present. As a result, a high dielectric constant can be imparted even to finely granulated barium titanate based crystal grains.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: April 10, 2012
    Assignee: Kyocera Corporation
    Inventor: Daisuke Fukuda
  • Publication number: 20120047472
    Abstract: A dummy-mesh-information creating unit separates a group of dummy metal blocks that are arranged in a pattern regularly staggered with respect to a direction of a wire object into meshes so that each mesh has the same layout of dummy metal blocks. An overlap determining unit determines whether a dummy metal block within a dummy mesh overlaps with the wire object. A dummy-information calculating unit calculates dummy information after any dummy metal block that is determined to be overlapped with the wire object is removed. An information integrating unit integrates the dummy information with information about the wire object, thereby generating a dummy-fill circuit layout. An evaluating unit evaluates whether the dummy-fill circuit layout satisfies the design criteria.
    Type: Application
    Filed: May 20, 2011
    Publication date: February 23, 2012
    Applicant: FUJITSU LIMITED
    Inventor: Daisuke FUKUDA
  • Patent number: 8107221
    Abstract: A dielectric ceramic includes crystal grains containing barium titanate as a main component, magnesium, a rare-earth element, and manganese, wherein the crystal grains have a cubic crystal structure; and the dielectric ceramic contains, per mole of barium, 0.033 to 0.085 mol of magnesium in terms of MgO, 0.1 to 0.2 mol of the rare-earth element (RE) in terms of RE2O3, and 0.006 to 0.018 mol of manganese in terms of MnO. Such a dielectric ceramic has a high relative dielectric constant, stable temperature characteristic of the relative dielectric constant, and no spontaneous polarization.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: January 31, 2012
    Assignee: Kyocera Corporation
    Inventors: Yusuke Azuma, Daisuke Fukuda
  • Patent number: 8104008
    Abstract: A layout design apparatus that limits the maximum wiring density and the maximum edge length of partial regions when determining wiring layout. After determining the wiring layout, the layout design apparatus inserts a dummy into a partial region having a low wiring density and thereby, the minimum wiring density and the minimum edge length of the partial regions are limited. Thus, the respective wiring densities and respective edge lengths of the partial regions are constrained within a constant range and irregularities in the substrate surface after polishing can be suppressed.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: January 24, 2012
    Assignee: Fujitsu Limited
    Inventor: Daisuke Fukuda
  • Patent number: 8097551
    Abstract: The invention relates to a ceramic dielectric material and to capacitors including the ceramic dielectric material. The ceramic dielectric material of the invention exhibits a high relative dielectric constant and a stable temperature characteristic of the relative dielectric constant.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: January 17, 2012
    Assignee: Kyocera Corporation
    Inventors: Kousei Kamigaki, Daisuke Fukuda
  • Publication number: 20120007637
    Abstract: A first driver device and a first diode are connected in parallel between an output node and a first voltage node. A second driver device and a second diode are connected in parallel between the output node and a second voltage node. When a first switching time comes, a first drive control section switches the first driver device from the off state to the on state after detecting that an output voltage at the output node reaches a predetermined first reference voltage. When a second switching time comes, the first drive control section switches the first driver device from the on state to the off state. A second drive control section switches the second driver device from the on state to the off state when the first switching time comes, and switches the second driver device from the off state to the on state when the second switching time comes.
    Type: Application
    Filed: July 7, 2011
    Publication date: January 12, 2012
    Inventor: Daisuke FUKUDA
  • Patent number: 8082536
    Abstract: A method for evaluating a process of manufacturing a semiconductor integrated circuit including a deposition step and a polishing step after the deposition step, the method includes: dividing the semiconductor integrated circuit into a plurality of areas; determining a deposition height after the deposition step for each of the areas; and determining a risk value for each of the areas on the basis of a difference in the deposition height between each of the areas and its adjacent areas.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: December 20, 2011
    Assignee: Fujitsu Limited
    Inventor: Daisuke Fukuda
  • Patent number: 8059388
    Abstract: The invention relates to a multilayer ceramic capacitor having dielectric layers and internal electrode layers disposed alternately. The dielectric layers include a dielectric ceramic containing barium titanate as a main component, and also calcium, magnesium, vanadium, manganese, and a rare-earth element. Crystals constituting the dielectric ceramic are constituted by grains containing barium titanate as their main component and containing calcium in a concentration of 0.2 atomic % or less or containing the calcium in a concentration of 0.4 atomic % or more. The crystals grains are also distinct in their relative distributions of magnesium and rare-earth elements between the center of the grain and the surface of the grain. Finally, the relative areas of the two kinds of crystals observed in the plane of a polished surface of the dielectric ceramic are described by a ratio b/(a+b), which is 0.5 to 0.8.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: November 15, 2011
    Assignee: Kyocera Corporation
    Inventors: Youichi Yamazaki, Hideyuki Osuzu, Yoshihiro Fujioka, Daisuke Fukuda
  • Publication number: 20110197173
    Abstract: A polishing estimation/evaluation device includes a dividing unit, an overpolished area extracting unit, and a dummy modifying unit. The dividing unit divides a layout of an integrated circuit into a plurality of partial areas. The overpolished area extracting unit refers to an overpolishing condition indicating whether overpolishing occurs in a vicinity of a partial area based on a wiring density in the partial area and a wiring density in surrounding areas of the partial area, and extracts a partial area where the overpolishing occurs from the plurality of partial areas obtained by the division by the dividing unit. The dummy modifying unit modifies dummy wiring in the partial area where the overpolishing occurs extracted by the overpolished area extracting unit and/or dummy wiring in surrounding areas of the partial area to reduce the number of partial areas where the overpolishing occurs.
    Type: Application
    Filed: February 2, 2011
    Publication date: August 11, 2011
    Applicant: FUJITSU LIMITED
    Inventor: Daisuke FUKUDA
  • Publication number: 20110144947
    Abstract: An online diagnostic system for a geothermal generation facility is discloses that includes: an automatic steam measurement device for measuring a characteristic of steam to be supplied to a steam turbine from a steam-water separator at the geothermal generation facility that outputs analysis data. A monitor•control device controls an operation of the geothermal generation facility while monitoring the geothermal generation facility. A diagnostic device performs at least one of an evaluation of a steam characteristic at the geothermal generation facility, an evaluation of the steam-water separator, and an evaluation of pulsation and confluence of a production well based on the analysis data from the automatic steam measurement device and performance data of the geothermal generation facility from the monitor•control device. An operating status of the geothermal generation facility is diagnosed.
    Type: Application
    Filed: October 19, 2009
    Publication date: June 16, 2011
    Applicants: FUJI ELECTRIC SYSTEMS CO., LTD., GEOTHERMAL ENGINEERING CO., LTD.
    Inventors: Ichiro Myougan, Toshikazu Kato, Isamu Osawa, Yasuyuki Hishi, Daisuke Fukuda, Yasuto Futagoishi, Toshiaki Aoki
  • Patent number: 7895986
    Abstract: A fuel injection nozzle for a diesel engine. The fuel injection nozzle may include a plurality of injection hole groups, each having two injection holes respectively. A distance between the two injection holes, an angle between longitudinal axes of the two injection holes and an angle between horizontal axes of said two injection holes of each injection hole group are each set such that fuel sprays injected from said two injection holes will form a single fuel spray cloud after the fuel sprays collide with a side wall of a combustion chamber formed in a top surface of a piston of the engine, and such that the distance between collision points of the fuel sprays will be in a predetermined range in which a penetration force of said fuel spray cloud along a longitudinal direction of said combustion chamber received after collision with said wall of said combustion chamber is at or near a predetermined maximum value.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: March 1, 2011
    Assignee: Mazda Motor Corporation
    Inventors: Daisuke Shimo, Masahiko Fujimoto, Motoshi Kataoka, Sangkyu Kim, Daisuke Fukuda
  • Publication number: 20110002073
    Abstract: An output buffer circuit of the present invention includes: a first output circuit having a first upper switching element and a first lower switching element, the first upper switching element having main terminals, one of the main terminals being maintained at a first voltage, the first lower switching element having main terminals, one of the main terminals being connected to the other main terminal of the upper switching element, the other main terminal of the first lower switching element being maintained at a second voltage, a portion where the other main terminal of the first upper switching element and one of the main terminals of the first lower switching element are connected to each other constituting an output portion for output to outside; a second output circuit having an output terminal connected to the output portion of the first output circuit; and a short-circuit detecting circuit configured to detect a short circuit of the output portion of the first output circuit.
    Type: Application
    Filed: September 17, 2010
    Publication date: January 6, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Daisuke FUKUDA, Tetsu Nagano, Takehiro Yano
  • Publication number: 20100188797
    Abstract: A crystal constituting a dielectric porcelain, comprised of a first crystal group composed of crystal grains of 0.2 atomic % or less calcium concentration and a second crystal group composed of crystal grains of 0.4 atomic % or more calcium concentration, wherein the ratio of concentration of each of magnesium and a first rare earth element contained in a center portion to that contained in a surface layer portion of crystal grains constituting the first crystal group is greater than the corresponding concentration ratio of crystal grains constituting the second crystal group, and wherein on a polished surface resulting from polishing of the surface of the dielectric porcelain, when the area of crystal grains of the first crystal group is referred to as a and the area of crystal grains of the second crystal group referred to as b, the ratio of b/(a+b) is in the range of 0.5 to 0.8.
    Type: Application
    Filed: November 29, 2007
    Publication date: July 29, 2010
    Applicant: KYOCERA CORPORATION
    Inventors: Youichi Yamazaki, Hideyuki Osuzu, Yoshihiro Fujioka, Daisuke Fukuda
  • Patent number: 7752579
    Abstract: A film thickness predicting apparatus compares a measurement value of a copper plating formed on wiring grooves of various patterns measured using a TEG and a film thickness of the copper plating calculated based on a plating model and a condition file. The film thickness predicting apparatus then delivers optimal plating model from the comparison result and calculates the film thickness of the copper plating formed on a substrate surface to be designed using the optimal plating model. The film thickness predicting apparatus enables to conduct a highly accurate film thickness predicting simulation.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: July 6, 2010
    Assignee: Fujitsu Limited
    Inventor: Daisuke Fukuda
  • Publication number: 20100152875
    Abstract: An estimation apparatus for estimating a formation of a plurality of wiring layers for an integrated circuit to be manufactured by laminating the wiring layers each formed through a deposition process of a wiring material on a substrate and subsequently polishing the deposited wiring material, the apparatus includes a deposition estimator, a polishing estimator, and an adjuster. The apparatus includes an optimizer configured to optimize distribution of the height of the wiring material for each of the wiring layers within an acceptable range by controlling the adjuster to generate various combinations of adjusted patterns of the wiring layers and by controlling the deposition estimator and the polishing estimator to perform estimation of distribution of deposition height of the wiring material and distribution of the wiring material to be remained after polishing for each of the wiring layers, respectively, for each of the combinations of the adjusted patterns.
    Type: Application
    Filed: December 7, 2009
    Publication date: June 17, 2010
    Applicant: FUJITSU LIMITED
    Inventor: Daisuke Fukuda
  • Publication number: 20100142120
    Abstract: A dielectric ceramic includes crystal grains containing barium titanate as a main component, magnesium, a rare-earth element, and manganese, wherein the crystal grains have a cubic crystal structure; and the dielectric ceramic contains, per mole of barium, 0.033 to 0.085 mol of magnesium in terms of MgO, 0.1 to 0.2 mol of the rare-earth element (RE) in terms of RE2O3, and 0.006 to 0.018 mol of manganese in terms of MnO. Such a dielectric ceramic has a high relative dielectric constant, stable temperature characteristic of the relative dielectric constant, and no spontaneous polarization.
    Type: Application
    Filed: October 26, 2007
    Publication date: June 10, 2010
    Applicant: KYOCERA Corporation
    Inventors: Yusuke Azuma, Daisuke Fukuda