Patents by Inventor Daisuke Imoto
Daisuke Imoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220105415Abstract: A training support system including an information acquisition unit configured to acquire trainee information including a symptom of a trainee, a database configured to store at least a plurality of symptoms and a plurality of training items in association with each other, an extraction unit configured to extract from the database one or more training items corresponding to the symptom of the trainee acquired by the information acquisition unit, and an output unit configured to output the one or more training items extracted from the database by the extraction unit.Type: ApplicationFiled: September 28, 2021Publication date: April 7, 2022Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takuya Iwata, Issei Nakashima, Hisataka Yuasa, Takeru Fukagawa, Takashi Shimizu, Yohei Otaka, Satoshi Hirano, Masaki Katoh, Yoko Inamoto, Daisuke Imoto
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Publication number: 20220108779Abstract: A rehabilitation assistance system, a rehabilitation assistance method, and a program capable of appropriately assisting rehabilitation are provided. A rehabilitation assistance system according to an embodiment includes: a storage unit configured to store, for each rehabilitation patient, evaluation indices of evaluation items regarding the evaluation items for evaluating a level of achievement of rehabilitation training; a processing unit configured to divide a plurality of rehabilitation patients into groups in accordance with the evaluation indices; and a display unit configured to update a display that shows a state of progress of a target patient in accordance with progress information of rehabilitation training and show the display.Type: ApplicationFiled: September 27, 2021Publication date: April 7, 2022Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takeru Fukagawa, Issei Nakashima, Hisataka Yuasa, Takuya Iwata, Takashi Shimizu, Yohei Otaka, Satoshi Hirano, Masaki Katoh, Daisuke Imoto, Shin Kitamura
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Publication number: 20220105390Abstract: A rehabilitation assistance system, a rehabilitation assistance method, and a program capable of appropriately assisting the rehabilitation are provided. A rehabilitation assistance system according to an embodiment includes: a first acquisition unit configured to acquire first information in accordance with a level of achievement of rehabilitation training performed by a rehabilitation patient in a first training apparatus; a second acquisition unit configured to acquire second information in accordance with a level of achievement of rehabilitation training performed by the rehabilitation patient in a second training apparatus which is different from the first training apparatus; and a display unit configured to display the first information and the second information in such a way that they are arranged close to each other.Type: ApplicationFiled: September 28, 2021Publication date: April 7, 2022Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Hisataka Yuasa, Issei Nakashima, Takeru Fukagawa, Takuya Iwata, Takashi Shimizu, Yohei Otaka, Satoshi Hirano, Masaki Katoh, Daisuke Imoto
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Publication number: 20220108780Abstract: A training support system including an information acquisition unit configured to acquire trainee information including a symptom of a trainee, a database configured to store a plurality of combinations of training experienced person information including a symptom of a training experienced person, a training performance, and a recovery status, a selection unit configured to select the training experienced person with the symptom similar to the symptom of the trainee acquired by the information acquisition unit from among a plurality of the training experienced persons, and an output unit configured to extract, from the database, at least any of the training performance and the recovery status of the training experienced person selected by the selection unit and then output at least any of the training performance and the recovery status.Type: ApplicationFiled: September 29, 2021Publication date: April 7, 2022Inventors: Hisataka Yuasa, Issei Nakashima, Takeru Fukagawa, Takuya Iwata, Takashi Shimizu, Yohei Otaka, Satoshi Hirano, Masaki Katoh, Daisuke Imoto, Shin Kitamura, Yoko Inamoto
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Patent number: 8918589Abstract: A memory controller (101) according to this invention includes: a command generation unit (102) which generates access commands each including a physical address, based on an access request including a logical address indicating a rectangular area in image data; and a command issuance unit (105) which issues, to a memory (0), the access commands generated by the command generation unit (102). The command generation unit (102) includes a group determination unit (104) which determines a group to which a bank including data to be accessed belongs, based on the physical address corresponding to the access request. The command generation unit (102) generates a pair of a first and a second access commands which share a prefetch buffer between two banks belonging to different groups, when data to be accessed is continuous across two banks belonging to different groups.Type: GrantFiled: April 21, 2009Date of Patent: December 23, 2014Assignee: Panasonic CorporationInventors: Koji Asai, Tetsuji Mochida, Daisuke Imoto, Takashi Yamada, Wataru Ohkoshi
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Patent number: 8738888Abstract: The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.Type: GrantFiled: September 14, 2012Date of Patent: May 27, 2014Assignee: Panasonic CorporationInventors: Takashi Yamada, Daisuke Imoto, Koji Asai, Nobuyuki Ichiguchi, Tetsuji Mochida
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Publication number: 20130013879Abstract: The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Applicant: PANASONIC CORPORATIONInventors: Takashi YAMADA, Daisuke IMOTO, Koji ASAI, Nobuyuki ICHIGUCHI, Tetsuji MOCHIDA
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Patent number: 8347026Abstract: A memory device according to this invention includes: N internal memory read buses and N internal memory write buses each including a plurality of internal slots; N memory modules; an output data bus and an input data bus each including a plurality of external slots; a read data processing unit which (i) selects, from pieces of data read from the N memory modules via the N internal memory read buses, pieces of data read via two or more internal slots, and (ii) provides the selected pieces of data to external slots of the output data bus; and a write data processing unit which provides each of pieces of data provided via the external slots included in the input data bus, to one of the internal slots included in the N internal memory write buses, so as to write the pieces of data to the N memory modules.Type: GrantFiled: December 18, 2008Date of Patent: January 1, 2013Assignee: Panasonic CorporationInventors: Takashi Yamada, Daisuke Imoto
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Patent number: 8307190Abstract: The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.Type: GrantFiled: December 25, 2007Date of Patent: November 6, 2012Assignee: Panasonic CorporationInventors: Takashi Yamada, Daisuke Imoto, Koji Asai, Nobuyuki Ichiguchi, Tetsuji Mochida
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Publication number: 20110167228Abstract: A memory device (10) according to this invention includes: N internal memory read buses (185) and N internal memory write buses (186) each including a plurality of internal slots (210); N memory modules (180); an output data bus (187) and an input data bus (188) each including a plurality of external slots (211); a Read data processing unit (150) which (i) selects, from pieces of data read from the N memory modules (180) via said N internal memory read buses (185), pieces of data read via two or more internal slots (210), and (ii) provides the selected pieces of data to external slots (211) of the output data bus (187); and a Write data processing unit (140) which provides each of pieces of data provided via the external slots (211) included in the input data bus (188), to one of the internal slots (210) included in the N internal memory write buses (186), so as to write the pieces of data to the N memory modules (180).Type: ApplicationFiled: December 18, 2008Publication date: July 7, 2011Applicant: PANASONIC CORPORATIONInventors: Takashi Yamada, Daisuke Imoto
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Publication number: 20110035559Abstract: A memory controller (101) according to this invention includes: a command generation unit (102) which generates access commands each including a physical address, based on an access request including a logical address indicating a rectangular area in image data; and a command issuance unit (105) which issues, to a memory (0), the access commands generated by the command generation unit (102). The command generation unit (102) includes a group determination unit (104) which determines a group to which a bank including data to be accessed belongs, based on the physical address corresponding to the access request. The command generation unit (102) generates a pair of a first and a second access commands which share a prefetch buffer between two banks belonging to different groups, when data to be accessed is continuous across two banks belonging to different groups.Type: ApplicationFiled: April 21, 2009Publication date: February 10, 2011Inventors: Koji Asai, Tetsuji Mochida, Daisuke Imoto, Takashi Yamada, Wataru Ohkoshi
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Patent number: 7780452Abstract: In a listening comprehension test using individual examination execution devices, according to the present invention, it is possible to avoid a dishonest act such as peeping at another examinee's answers. An individual examination execution device (101) reads examination question data and individual information from an examination question storage means (102) storing the examination questions and an individual information storage means (103) storing the individual information, respectively. Further, the individual examination device selectively generates actual questions according to the individual information read by an actual question generation means (104), and reproduces the actual questions by a reproduction means (105), thereby preventing dishonest acts of respective examinees.Type: GrantFiled: October 17, 2005Date of Patent: August 24, 2010Assignee: Panasonic CorporationInventors: Kohei Okada, Katsuhiro Nakai, Takehisa Hirano, Kouji Mukai, Tomoaki Tezuka, Daisuke Imoto
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Publication number: 20100030980Abstract: The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.Type: ApplicationFiled: December 25, 2007Publication date: February 4, 2010Applicant: PANASONIC CORPORATIONInventors: Takashi Yamada, Daisuke Imoto, Koji Asai, Nobuyuki Ichiguchi, Tetsuji Mochida
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Publication number: 20080020366Abstract: In a listening comprehension test using individual examination execution devices, it is possible to avoid a dishonest act such as peeping at another examinee's answers. In an individual examination execution device (101), examination question data and individual information are read from an examination question storage means (102) that stores the examination questions and an individual information storage means (103) that stores the individual information, respectively, and actual questions that are selectively generated according to the individual information read by an actual question generation means (104) are reproduced by a reproduction means (105), thereby preventing dishonest acts of the respective examinees.Type: ApplicationFiled: October 17, 2005Publication date: January 24, 2008Inventors: Kohei Okada, Katsuhiro Nakai, Takehisa Hirano, Kouji Mukai, Tomoaki Tezuka, Daisuke Imoto