Patents by Inventor Daisuke Itou
Daisuke Itou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8090912Abstract: A request issued by the CPU is output from the local arbiter by way of the CPU bus and the CPU-issued request queue. The cache replacement request loop-back circuit determines at the loop-back determination circuit whether the outputted request is a cache replacement request or not. A request other than a cache replacement request is output onto the local bus. A cache replacement request is output to the selector and sent to the request handling section when there is no valid request on the global bus.Type: GrantFiled: April 24, 2007Date of Patent: January 3, 2012Assignee: Fujitsu LimitedInventors: Takaharu Ishizuka, Toshikazu Ueki, Makoto Hataida, Takashi Yamamoto, Yuka Hosokawa, Takeshi Owaki, Daisuke Itou
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Publication number: 20110309868Abstract: A transmission LSI calculates a buffer usage rate in accordance with data stored in a buffer in a transmission data processing unit and determines, in accordance with the calculated buffer usage rate, the number of signal lines that perform a phase readjustment and the timing thereof. Then, the transmission LSI and a receiving LSI perform a phase adjustment using some of the signal lines and continues a data transfer using the rest of the signal lines. Accordingly, it is possible to maintain the optimum phase of a clock without delaying the data transfer.Type: ApplicationFiled: September 1, 2011Publication date: December 22, 2011Applicant: FUJITSU LIMITEDInventors: Shintaro ITOZAWA, Hiroshi NAKAYAMA, Junji ICHIMIYA, Daisuke ITOU
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Patent number: 8078920Abstract: An information processing device having two processing units capable of operating in synchronization with each other, includes: a common unit capable of outputting an identical signal to the two processing units; detection units that are respectively provided for the processing units and each detects errors occurred in corresponding processing unit respectively; a comparison unit that compares outputs from the two processing units; and a control unit that controls signals from the processing units to the common unit, based on a detection result of the detection units and a comparison result of the comparison unit, and determines, if errors of an identical type are simultaneously detected by the detection units, that the errors are due to an error of the common unit.Type: GrantFiled: September 4, 2009Date of Patent: December 13, 2011Assignee: Fujitsu LimitedInventors: Atsushi Morosawa, Takaharu Ishizuka, Toshikazu Ueki, Makoto Hataida, Yuka Hosokawa, Takeshi Owaki, Takashi Yamamoto, Daisuke Itou
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Patent number: 8065566Abstract: A control device managing a plurality of nodes transmitting and receiving data containing an error correcting code, comprises means accepting, when any one of the nodes detects an uncorrectable error from the data containing the error correcting code, a signal transmitted by the node detecting the error, means judging from a record of the detection of a first node, when accepting the signal from a second node receiving data transmitted by the first node, whether or not the first node has detected the uncorrectable error from the data transmitted to the second node, and means stopping, when the first node has detected the uncorrectable error from the data transmitted to the second node, a process attributed to the acceptance of the signal from the second node.Type: GrantFiled: April 19, 2007Date of Patent: November 22, 2011Assignee: Fujitsu LimitedInventors: Takashi Yamamoto, Takaharu Ishizuka, Toshikazu Ueki, Makoto Hataida, Yuka Hosokawa, Takeshi Owaki, Daisuke Itou
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Publication number: 20110080397Abstract: A backlight drive apparatus for current driving a plurality of strings has a period in which at least one of the strings is a current driven idly during a liquid crystal OFF period, in addition to a current driving period in which video information is displayed via liquid crystals. A failure detection section can monitor stabilized detection voltages in the period when current driven idly and detects failure state of the backlight panel.Type: ApplicationFiled: June 23, 2010Publication date: April 7, 2011Applicant: Panasonic CorporationInventors: Yasunori Yamamoto, Shinichiro Kataoka, Tsukasa Kawahara, Go Takata, Ryuji Ueda, Daisuke Itou
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Patent number: 7873789Abstract: In a system controller including a CPU-issued request queue having a circuit that processes plural requests having identical addresses not to be inputted to the CPU-issued request queue, a latest request other than a cache replace request is retained by an input-request retaining section. Consequently, even if an address of an issued request for cache replace request matches an address of a request retained by the CPU-issued request queue, the issued request for the cache replace request is not retried but is queued in the CPU-issued request queue when the address of the issued request for the cache replace request does not match the entire address retained by the input-request retaining section.Type: GrantFiled: April 24, 2007Date of Patent: January 18, 2011Assignee: Fujitsu LimitedInventors: Takaharu Ishizuka, Toshikazu Ueki, Makoto Hataida, Takashi Yamamoto, Yuka Hosokawa, Takeshi Owaki, Daisuke Itou
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Patent number: 7862238Abstract: A hydrodynamic bearing rotary device which can reduce rotation friction, and recording and reproducing apparatus including the same is provided. In the hydrodynamic bearing rotary device, such as hard disc devices, a rotary shaft having a hub on one end is provided in a bearing of a sleeve so as to be rotatable. Thrust hydrodynamic grooves are provided on the other end surface of the rotary shaft, to form a thrust bearing with the thrust plate. A communication path is provided in the sleeve. The second gap between the hub and the sleeve end surface is used as a flow channel and is connected to the communication path. In this way, the rotation friction torque of the thrust bearing can be made sufficiently small, and internal pressure in bonded portions of the rotary shaft or the bottom plate can be suppressed. Thus, the oil can be prevented from oozing out from a small space of the bonded surfaces. Furthermore, the hydrodynamic bearing can be made thin.Type: GrantFiled: March 29, 2007Date of Patent: January 4, 2011Assignee: Panasonic CorporationInventors: Takafumi Asada, Hiroaki Saito, Daisuke Itou, Keigo Kusaka, Hiroyuki Kiriyama
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Publication number: 20100275084Abstract: A transmitting circuit transmits data to which an error detection code is attached to a receiving circuit via a transmission path. When detecting the error of the data received via the transmission path, a receiving circuit transmits a retransmit request for the data in which the error is detected to the transmitting circuit. The receiving circuit enters a termination unit adjustment period using the error detection of the received data as a trigger and updates the resistance values of a receiving side termination unit installed at the termination of the transmission path to an appropriate value within the termination unit adjustment period.Type: ApplicationFiled: April 20, 2010Publication date: October 28, 2010Applicant: FUJITSU LIMITEDInventors: Junji Ichimiya, Hiroshi Nakayama, Daisuke Itou, Shintaro Itozawa
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Publication number: 20100245365Abstract: An image generation system includes an operation information acquisition section that acquires operation information based on sensor information from a controller that includes a sensor, the operation information acquisition section acquiring rotation angle information about the controller around a given coordinate axis as the operation information, a hit calculation section that performs a hit calculation process, the hit calculation process setting at least one of a moving state and an action state of a hit target that has been hit by a hit object based on the rotation angle information that has been acquired by the operation information acquisition section, and an image generation section that generates an image based on the operation information.Type: ApplicationFiled: March 26, 2010Publication date: September 30, 2010Applicant: NAMCO BANDAI GAMES INC.Inventors: Yoshikazu HATO, Daisuke ITOU
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Patent number: 7779209Abstract: In a multiprocessor system, a system controller includes snoop tags which are copy information on cache tags retained by respective CPUs. If the same address is registered in S (Shared state) in the cache tag of each of the CPUs connected to the same CPU bus, the address is registered in S (Shared state) in only any one of the snoop tags corresponding to the CPUs in which the same address is registered.Type: GrantFiled: April 24, 2007Date of Patent: August 17, 2010Assignee: Fujitsu LimitedInventors: Takaharu Ishizuka, Toshikazu Ueki, Makoto Hataida, Takashi Yamamoto, Yuka Hosokawa, Takeshi Owaki, Daisuke Itou
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Publication number: 20100191942Abstract: A northbridge, when detecting a synchronization break of a redundant CPU, stops the operation of an abnormal CPU bus where an error has occurred and the firmware in an FWH instructs the northbridge to inhibit an external instruction. In addition, the firmware save the inside information of a normal CPU connected to a normal CPU bus and cache data on a memory and the northbridge issues reset to all CPUs in the home system board. The firmware then restores the inside information of the CPU save on the memory to the all CPUs and instructs the northbridge to cancel the inhibition of the external instruction.Type: ApplicationFiled: March 24, 2010Publication date: July 29, 2010Applicant: FUJITSU LIMITEDInventors: Takeshi Owaki, Takaharu Ishizuka, Toshikazu Ueki, Makoto Hataida, Yuka Hosokawa, Atsushi Morosawa, Takashi Yamamoto, Daisuke Itou
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Patent number: 7711899Abstract: An information processing device of a multiprocessor configuration that can increase significantly the processing capability of read requests. The information processing device comprises a plurality of processing units, a plurality of cache memories for storing temporarily the data read by the plurality of processing units from respective main memories in combination with tag information indicating the state of the data that will be stored, and a system controller for controlling the access of the plurality of processing units to the main memories. The system controller comprises a tag copy unit for holding a copy of the tag information that will be stored in the cache memory, a plurality of write cues for storing write requests, and a store buffer for storing the arbitration results relating to a plurality of write requests that will be stored in the plurality of write cues.Type: GrantFiled: June 30, 2005Date of Patent: May 4, 2010Assignee: Fujitsu LimitedInventors: Takaharu Ishizuka, Daisuke Itou, Takashi Yamamoto
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Patent number: 7694106Abstract: A multiprocessor system includes a judging unit judging whether a read command inputted to a global address crossbar is a read command to a memory on an own system board, an executing unit speculatively executing, when the judging unit judges that the read command is a read command to the memory on the own system board, the read command before global access based on an address notified from the global address crossbar, a setting unit setting for queuing data read from the memory in a data queue provided on a CPU without queuing the data in a data queue provided on the memory, and an instructing unit instructing, based on notification from the global address crossbar, the data queue provided on the CPU to discard the data or transmit the data to the CPU.Type: GrantFiled: April 20, 2007Date of Patent: April 6, 2010Assignee: Fujitsu LimitedInventors: Toshikazu Ueki, Takaharu Ishizuka, Makoto Hataida, Takashi Yamamoto, Yuka Hosokawa, Takeshi Owaki, Daisuke Itou
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Publication number: 20100077262Abstract: An information processing device having two processing units capable of operating in synchronization with each other, includes: a common unit capable of outputting an identical signal to the two processing units; detection units that are respectively provided for the processing units and each detects errors occurred in corresponding processing unit respectively; a comparison unit that compares outputs from the two processing units; and a control unit that controls signals from the processing units to the common unit, based on a detection result of the detection units and a comparison result of the comparison unit, and determines, if errors of an identical type are simultaneously detected by the detection units, that the errors are due to an error of the common unit.Type: ApplicationFiled: September 4, 2009Publication date: March 25, 2010Applicant: FUJITSU LIMITEDInventors: Atsushi MOROSAWA, Takaharu ISHIZUKA, Toshikazu UEKI, Makoto HATAIDA, Yuka HOSOKAWA, Takeshi OWAKI, Takashi YAMAMOTO, Daisuke ITOU
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Publication number: 20100060177Abstract: The load driving apparatus according to the present invention includes a load current setting signal generating section, a load current generating section, a reference voltage generating section and a drive voltage generating section. The load current setting signal generating section generates a desired load current setting signal. The load current generating section generates a load current based on the load current setting signal to drive the load. The reference voltage generating section generates a reference voltage based on the load current setting signal. The drive voltage generating section generates a drive voltage, supplies the drive voltage to the load, generates a between-both-terminals voltage between both terminals of the load current generating section based on the drive voltage and controls the drive voltage so that the difference between the between-both-terminals voltage and the reference voltage becomes small.Type: ApplicationFiled: September 3, 2009Publication date: March 11, 2010Applicant: Panasonic CorporationInventors: Go TAKATA, Shinichiro Kataoka, Yasunori Yamamoto, Tsukasa Kawahara, Ryuji Ueda, Daisuke Itou
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Patent number: 7674043Abstract: An object of the present invention is to provide a hydrodynamic bearing type rotary device which can improve rotation performance, suppress a friction torque, and reduce power consumption of motor, and a recording and reproducing apparatus including the same. A shaft having a flange on one end and a hub on the other end is provided with a bearing of a sleeve so as to be rotatable. The sleeve includes a communication hole. A third gap between the hub and the sleeve end surface is a flow path, and is connected to the communication hole. Provided that a first gap between a thrust plate 4 and the flange 3 is S1, a second gap between the flange 3 and a lower end surface of the sleeve 1 is S2, and a third gap between the upper end surface of the sleeve 1 and the hub 7 is S3, widths of the gaps satisfy the relational expression, S3>(S1+S2).Type: GrantFiled: March 19, 2007Date of Patent: March 9, 2010Assignee: Panasonic CorporationInventors: Takafumi Asada, Hiroaki Saito, Daisuke Itou, Hiroyuki Kiriyama, Tomoharu Takeda
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Publication number: 20100052572Abstract: The N light emitting element groups each include one or more light emitting elements. The power source circuit includes a control input terminal and supplies the power source voltage to the N light emitting element groups. The N current driving circuits, each including a feedback output terminal, generate N drive currents for driving the respective N light emitting element groups and generate main feedback voltages at the feedback output terminals based on the power source voltage. The main feedback circuit applies a main feedback signal to the control input terminal based on the N main feedback voltages. The auxiliary feedback circuit applies an auxiliary feedback signal to the control input terminal based on the power source voltage. The power source circuit adjusts the power source voltage based on at least one of the main feedback signal and the auxiliary feedback signal.Type: ApplicationFiled: August 27, 2009Publication date: March 4, 2010Applicant: Panasonic CorporationInventors: Shinichiro KATAOKA, Ryuji UEDA, Go TAKATA, Daisuke ITOU, Yasunori YAMAMOTO, Tsukasa KAWAHARA
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Patent number: 7395489Abstract: A memory control device includes a writing unit writing information to a memory module, a reading unit reading the information from the memory module, an error detecting unit executing a detection of an error in the formation in parallel with the reading operation by the reading unit, an error correcting unit correcting the error in the information containing the error detected, and a control unit controlling a transfer and a receipt of the information to and from an external device and stopping, when the error is detected, an output of the information to the external device.Type: GrantFiled: January 13, 2003Date of Patent: July 1, 2008Assignee: Fujitsu LimitedInventors: Daisuke Itou, Masaki Ukai
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Publication number: 20080046694Abstract: A multiprocessor system includes a judging unit judging whether a read command inputted to a global address crossbar is a read command to a memory on an own system board, an executing unit speculatively executing, when the judging unit judges that the read command is a read command to the memory on the own system board, the read command before global access based on an address notified from the global address crossbar, a setting unit setting for queuing data read from the memory in a data queue provided on a CPU without queuing the data in a data queue provided on the memory, and an instructing unit instructing, based on notification from the global address crossbar, the data queue provided on the CPU to discard the data or transmit the data to the CPU.Type: ApplicationFiled: April 20, 2007Publication date: February 21, 2008Applicant: Fujitsu LimitedInventors: Toshikazu Ueki, Takaharu Ishizuka, Makoto Hataida, Takashi Yamamoto, Yuka Hosokawa, Takeshi Owaki, Daisuke Itou
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Publication number: 20080046664Abstract: To prevent a decrease in performance of controlling a snoop tag. A queue is stored with REPLACE target WAY information and an index as an entry associated with a REPLACE request received from a processor, the index stored in the queue is compared with an index of a subsequent READ request, and, as a result of the comparison, a process based on the index-coincident READ request is executed with respect to the snoop tag corresponding to a content of a cache memory of the processor. Further, the REPLACE target WAY information of the READ request is replaced with the WAY information in the index-coincident entry within the queue.Type: ApplicationFiled: April 24, 2007Publication date: February 21, 2008Applicant: FUJITSU LIMITEDInventors: Makoto Hataida, Toshikazu Ueki, Takaharu Ishizuka, Takashi Yamamoto, Yuka Hosokawa, Takeshi Owaki, Daisuke Itou