Abstract: A pulling detection device includes: a base in which, on a foundation portion, a first wall portion, a projection, and a second wall portion are provided; a movable rod including a switch operation body and a pulling rod, the switch operation body having a first wall portion opposed surface, a projection opposed surface, and a second wall portion opposed surface, the pulling rod extending from the second wall portion opposed surface, while movement of the movable rod toward one side is restricted by contact between the first wall portion and the first wall portion opposed surface and movement of the movable rod toward another side is restricted by contact between the projection and the projection opposed surface; an elastic body provided between the second wall portion opposed surface and the second wall portion; a first switch which operates by contact/separation; and a second switch which operates by contact/separation.

Abstract: An interface circuit for supplying a plurality of data signals to a data reception circuit includes a timing signal generating circuit configured to generate a timing signal. The timing signal indicates a timing to switch operation of the interface circuit between a data input mode and a non-input mode. The interface circuit further includes a data control circuit configured to control a supply of the data signals to the data reception circuit in the data input mode, a plurality of abnormality detection circuits each configured to detect an abnormality that has occurred in the data reception circuit, and a select circuit configured to select one abnormality detection circuit based on each of the data signals supplied in the non-input mode of the interface circuit, and output, as an abnormality detection signal, a detection result of the selected one of the abnormality detection circuits.

Abstract: An interface circuit for supplying a plurality of data signals to a data reception circuit includes a timing signal generating circuit configured to generate a timing signal. The timing signal indicates a timing to switch operation of the interface circuit between a data input mode and a non-input mode. The interface circuit further includes a data control circuit configured to control a supply of the data signals to the data reception circuit in the data input mode, a plurality of abnormality detection circuits each configured to detect an abnormality that has occurred in the data reception circuit, and a select circuit configured to select one abnormality detection circuit based on each of the data signals supplied in the non-input mode of the interface circuit, and output, as an abnormality detection signal, a detection result of the selected one of the abnormality detection circuits.

Abstract: A synchronous processing system having semiconductor integrated circuits. One of the semiconductor integrated circuits as a master chip includes a first synchronization controller and a first counter controller that allows a counter in the master chip to perform counting synchronously with a clock pulse in response to a synchronization control signal from the first synchronization controller. Another semiconductor integrated circuit as a slave chip includes a second synchronization controller that receives the synchronization control signal from the master chip, and a second counter controller that allows a counter in the slave chip to perform counting synchronously with the clock pulse in response to the synchronization control signal received. Each of the first and second counter controllers allows the counter to stop counting if the synchronization control signal is not supplied at the time point that a count value of the counter has reached a predetermined value.

Abstract: An input signal is segmented by a first data latch into 2 bit segments according to rising and falling edges of a clock signal clk, and latched. When the input signal is an RSDS signal, 2 sets worth of 2 bit data are latched according to rising and falling edges of a clock signal clkx2, using a first output section, a first data holding section, and a second output section. When the input signal is a mini-LVDS signal, 4 clock cycles worth of data are held according to the rising and falling edges of the clock signal clkx2 using the first data holding section and the second output section. One set's worth of 8 bit data is then latched according to a rising edge of a clock signal clkx4 using the first output section, a third output section, a fourth output section, and a fifth output section.

Abstract: A synchronous processing system having semiconductor integrated circuits. One of the semiconductor integrated circuits as a master chip includes a first synchronization controller and a first counter controller that allows a counter in the master chip to perform counting synchronously with a clock pulse in response to a synchronization control signal from the first synchronization controller. Another semiconductor integrated circuit as a slave chip includes a second synchronization controller that receives the synchronization control signal from the master chip, and a second counter controller that allows a counter in the slave chip to perform counting synchronously with the clock pulse in response to the synchronization control signal received. Each of the first and second counter controllers allows the counter to stop counting if the synchronization control signal is not supplied at the time point that a count value of the counter has reached a predetermined value.

Abstract: A synchronous processing system having semiconductor integrated circuits. One of the semiconductor integrated circuits as a master chip includes a first synchronization controller and a first counter controller that allows a counter in the master chip to perform counting synchronously with a clock pulse in response to a synchronization control signal from the first synchronization controller. Another semiconductor integrated circuit as a slave chip includes a second synchronization controller that receives the synchronization control signal from the master chip, and a second counter controller that allows a counter in the stave chip to perform counting synchronously with the clock pulse in response to the synchronization control signal received. Each of the first and second counter controllers allows the counter to stop counting if the synchronization control signal is not supplied at the time point that a count value of the counter has reached a predetermined value.

Abstract: Input signal is segmented by first data latch into 2 bit segments according to rising edge and falling edge of a clock signal clk, and latched. When the input signal is an RSDS signal, 2 sets worth of 2 bit data are latched according to rising edge and falling edge of a clock signal clkx2, using a first output section, a first data holding section, and a second output section. When the input signal is a mini-LVDS signal, 4 clock cycles worth of data is held according to rising edge and falling edge of the clock signal clkx2 using the first data holding section and the second output section. 1 set's worth of 8 bit data is then latched according to rising edge of a clock signal clkx4 using the first output section, a third output section, a fourth output section, and a fifth output section.

Abstract: A data transfer circuit includes primary data holding circuits that hold input data according to a first clock pulse signal and output data being held; and secondary data holding circuits that hold the output data of the primary data holding circuits according to a second clock pulse asynchronous to the first clock pulse and output data being held. Pulse signal generator generates a pulse signal synchronous with the second clock pulse signal when a pulse edge of the first clock pulse signal and a pulse edge of the second clock pulse signal occur at different timings and generates a pulse signal having the pulse edge the second clock pulse signal removed therefrom when the pulse edge of the the first clock pulse signal and the pulse edge of the the second clock pulse signal occur at the same timing. The secondary data holding circuits hold the output data of the primary data holding circuits synchronously with the pulse signal generated by the pulse signal generator.

Abstract: An output driver includes a data processing unit configured to perform a data processing on an input signal to generate processing result data; a D/A (Digital-to-Analog) conversion unit configured to apply D/A conversion on the processing result data to generate an analog signal; an output amplifier configured to amplify the analog signal to obtain an amplified analog signal as an output signal; a comparing unit configured to compare the processing result data with expected value data to obtain and output comparison result data; and an output control unit configured to select the comparison result data as the output signal instead of the amplified analog signal according to a comparison output selection signal.

Abstract: A data transfer circuit includes primary data holding circuits that hold input data according to a first clock pulse signal and output data being held; and secondary data holding circuits that hold the output data of the primary data holding circuits according to a second clock pulse asynchronous to the first clock pulse and output data being held. Pulse signal generator generates a pulse signal synchronous with the second clock pulse signal when a pulse edge of the first clock pulse signal and a pulse edge of the second clock pulse signal occur at different timings and generates a pulse signal having the pulse edge the second clock pulse signal removed therefrom when the pulse edge of the the first clock pulse signal and the pulse edge of the the second clock pulse signal occur at the same timing. The secondary data holding circuits hold the output data of the primary data holding circuits synchronously with the pulse signal generated by the pulse signal generator.

Abstract: A synchronous processing system having semiconductor integrated circuits. One of the semiconductor integrated circuits as a master chip comprises a first synchronization controller and a first counter controller that allows a counter in the master chip to perform counting synchronously with a clock pulse in response to a synchronization control signal from the first synchronization controller. Another semiconductor integrated circuit as a slave chip comprises a second synchronization controller that receives the synchronization control signal from the master chip, and a second counter controller that allows a counter in the slave chip to perform counting synchronously with the clock pulse in response to the synchronization control signal received. Each of the first and second counter controllers allows the counter to stop counting if the synchronization control signal is not supplied at the time point that a count value of the counter has reached a predetermined value.

Abstract: A memory control circuit in a memory chip includes a selection controller that can switch the memory chip between selected and deselected states. The selection controller sends and receives access wait signals to and from at least one other memory chip. One access wait signal indicates that the selection controller has placed the memory chip in the deselected state. Another access wait signal, when received, causes the selection controller to place the memory chip in the selected state. A set of memory chips including this memory control circuit can shift access among themselves without receiving control signals from an external device. The external device can accordingly access the memory chips with minimal delays and minimal overhead.

Abstract: An access control device having a number-of-waits setting circuit determining a wait periodicity corresponding to an operating speed of peripheral devices connected to a second bus according to an address corresponding to an access request to the second bus sent from a first bus, responsive to the access request, and a count value generator generating a count value up to the wait periodicity set to the number-of-waits setting circuit. A control signal holding circuit holds a control signal for holding a state of the second bus at the setting of the wait periodicity by the number-of-waits setting circuit during a count period of the count value generator and maintains the access state of the status controller. A clock control circuit divides a clock for the first bus according to the wait periodicity set and outputs the result of division to the second bus.

Abstract: A memory control circuit in a memory chip includes a selection controller that can switch the memory chip between selected and deselected states. The selection controller sends and receives access wait signals to and from at least one other memory chip. One access wait signal indicates that the selection controller has placed the memory chip in the deselected state. Another access wait signal, when received, causes the selection controller to place the memory chip in the selected state. A set of memory chips including this memory control circuit can shift access among themselves without receiving control signals from an external device. The external device can accordingly access the memory chips with minimal delays and minimal overhead.

Abstract: An access control device which includes a number-of-waits setting circuit for determining a wait periodicity corresponding to an operating speed of each of peripheral devices connected to a second bus according to an address corresponding to an access request to the second bus sent from a first bus, in response to the access request, and a count value generator for generating a count value up to the wait periodicity set to the number-of-waits setting circuit. The device also includes a control signal holding circuit for holding a control signal for holding a state of the second bus at the setting of the wait periodicity by the number-of-waits setting circuit during a count period of the count value generator and maintaining the access state of the status controller, and a clock control circuit for dividing a clock for the first bus according to the wait periodicity set to the number-of-waits setting circuit and outputting the result of division to the second bus.

Abstract: A driver circuit keeps optical power from other normal light emitting elements, even if either of multiple light emitting elements has disconnection fault. The driver circuit has series connected multiple light emitting elements, which are connected to a constant current power source and a multiple light emitting power control circuits for controlling light emitting power of the corresponding light emitting elements.